KR950006471B1 - Semiconductor memory cell - Google Patents

Abstract

No content.

Description

Semiconductor memory cell

1A to 1J are schematic cross-sectional views for explaining a manufacturing process of a ferroelectric memory cell according to one embodiment of the present invention.

FIG. 2 is a top view of the ferroelectric memory cell of FIG. 1j. FIG.

3A to H are schematic cross-sectional views for explaining a manufacturing process of a ferroelectric memory cell according to the prior art.

4 is a top view of the ferroelectric memory cell of FIG. 3h.

5A and 5B are diagrams for explaining inversion of spontaneous polarization in PZT.

6 is a cross-sectional view for explaining stress concentration in a ferroelectric film including a curved surface.

* Explanation of symbols for main parts of the drawings

2: separation area 21: semiconductor substrate

23 gate insulating film 24 word line

25 source / drain region 27 lower capacitor electrode

28 ferroelectric film 29 upper capacitor electrode

30 interlayer insulating film 31 bit line

32: wiring layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell of one transistor, one capacitor type, and more particularly to an improvement of a semiconductor memory cell (hereinafter referred to as a "ferroelectric memory cell") including a capacitor using a ferroelectric film.

3a to h are described in the 1989 IEEE International Solid-state Circuits Conference; Digest of Technical Papers PP.242-243 is a schematic cross-sectional view illustrating the manufacturing process of ferroelectric memory cells.

Referring to FIG. 3A, a field oxide film 2 for separation is formed on a semiconductor substrate 1 of silicon.

Referring to FIG. 3B, the gate insulating film 3 is formed by thermal oxidation.

On the gate insulating film 3, a word line 4 serving as a gate electrode is formed.

The word line 4 can be formed by depositing a polysilicon layer containing impurities so as to have conductivity by LPCVD (Low-Pressure Chemical Vapor Deposition) and patterning the polysilicon layer by photolithography.

Referring to FIG. 3C, using the gate electrode 4 and the isolation region 2 as a mask, the source / drain regions 5 are formed in self-alignment by ion implantation.

Referring to FIG. 3D, the gate electrode 4 and the source / drain regions 5 are covered with the first interlayer insulating film 6.

Referring to FIG. 3E, the lower capacitor electrode 7 is formed on the first interlayer insulating film 6 above the gate electrode 4.

The lower capacitor electrode 7 can be formed by depositing a conductive layer on the first interlayer insulating film 6 by sputtering or the like and patterning the conductive layer.

Thereafter, the lower capacitor electrode 7 is covered by the capacitor dielectric film 8.

The capacitor dielectric film 8 can be formed by depositing a ferroelectric film by a sputtering method or a sol-gel method, followed by patterning after proper heat treatment.

Referring to FIG. 3F, the upper capacitor electrode 9 is formed on the capacitor dielectric film 8.

The upper capacitor electrode 9 may be formed by sputtering and photolithography.

The upper capacitor electrode 9 is covered by the second interlayer insulating film 10.

Referring to FIG. 3G, each of the contact holes 5a and 9a for enabling electrical connection to the source / drain region 5 and the upper capacitor electrode 9 is formed by the interlayer insulating film 6, by photolithography. 10) to penetrate through.

Referring to FIG. 3h, a wiring for connecting the other one of the source / drain region 5 to the upper capacitor electrode while the bit line 11 connected to one of the source / drain regions 5 is formed. (12) is formed.

The bit line 11 and the wiring 12 can be formed by depositing and patterning a conductive layer so as to cover the interlayer insulating film 10 and the contact holes 5a and 9a.

Finally, a surface protective film (not shown) is provided to complete the ferroelectric film memory cell.

Referring to FIG. 4, the top pattern of the ferroelectric memory cell of FIG. 3h is shown.

FIG. 3H corresponds to the cross section along the line 3H-3H in FIG.

However, a ferroelectric means that (1) it has a finite spontaneous polarization when the external electric field is zero, and (2) when the external electric field is applied, the direction of the spontaneous polarization can be reversed in response to the direction of the external electric field. It can be defined as a substance.

Storing two values of information in the ferroelectric film means changing the polarization direction of the ferroelectric film in correspondence with "0" and "1" of the input information.

Specifically, in FIG. 3H, when voltage is applied such that the lower capacitor electrode 7 is 5V and the upper capacitor electrode 9 is 0V, the spontaneous polarization of the ferroelectric film 8 is moved from the lower cathode to the upper anode. Are arranged to face.

Conversely, when a voltage is applied such that the lower capacitor electrode 7 is 0V and the upper capacitor electrode 9 is 5V, the spontaneous polarization of the ferroelectric film 8 is arranged from the upper cathode to the lower anode.

5A and b, the inversion of the spontaneous polarization in so-called PZT, which is one of the ferroelectric materials, is illustrated.

PZT has a perovskite crystal structure as shown in these figures, and is represented by chemical formula.

Namely, the atom A corresponds to Pb, the atom B represents Ti or Zr, and the atom O represents oxygen.

In the state shown in FIG. 5A, the atom B is slightly displaced upward from the center of the unit lattice, and the spontaneous polarization of PZT is directed from the lower cathode to the upper anode as indicated by the arrow.

As shown in FIG. 5B, the atom B can be displaced slightly downward from the center of the unit grid by applying an external electric field.

As a result, the spontaneous polarization of PZT is reversed from the upper cathode toward the lower anode as indicated by the arrow.

During this inversion of the spontaneous polarization, all atoms in the unit lattice move little by little to allow the movement of the electron B, and the unit lattice once extends in the direction of polarization.

That is, the crystal of PZT expands and contracts in the direction of the polarization whenever the spontaneous polarization is reversed.

On the other hand, expansion and contraction of PZT crystals in a direction perpendicular to the direction of spontaneous polarization is slight.

This causes some problems when the ferroelectric film contains a curved surface.

Referring to FIG. 6, a cross section of a capacitor formed over an area above the gate electrode 4 is shown.

The capacitor of FIG. 6 may have a large area, but the ferroelectric film 8 includes a curved surface having a relatively large curvature in the stepped portion S indicated by the round mark of the dotted line.

Each time the spontaneous polarization is reversed by the upper and lower capacitor electrodes 9 and 7, the ferroelectric film 8 is stretched in the film thickness direction as indicated by the arrow.

Therefore, at the time of expansion and contraction, the ferroelectric film 8 is subjected to mechanical stress concentration in the stepped portion S, and there is a fear that the stepped portion S is fatigue-broken after a large number of spontaneous polarization inversions.

Therefore, the capacitor including the ferroelectric film is preferably formed on a substantially flat surface.

In the ferroelectric memory cell of FIG. 3H, since the bit lines 11 and the wirings 12 are arranged on both sides of the gate electrode 4, it is possible to form the ferroelectric film 8 flat. Is confined to a narrow area of the top.

Therefore, when the dimension of the memory cell shown in FIG. 3h is reduced, the width of the gate electrode 4 is also reduced. Therefore, the area of the ferroelectric film 8 must also be reduced.

Therefore, the capacitor capacity including the ferroelectric film 8 is lowered, and if the capacity is 50 fc or less, the stable operation of the memory cannot be guaranteed.

In view of the problems of the prior art, an object of the present invention is to provide a semiconductor device having a ferroelectric type memory cell capable of providing a flat and large area ferroelectric film.

According to one aspect of the present invention for achieving the above object, a semiconductor memory cell having one field effect transistor and one capacitor includes: a semiconductor substrate; First and second source / drain regions formed on the main surface of the semiconductor substrate, the first and second source / drain regions being spaced apart from each other so as to form a channel region between the first and second source / drain regions; A gate insulating film formed over the channel region; A gate electrode formed over said channel region via said gate insulating film and formed by a portion of a word line; A bit line formed over said main surface of said semiconductor substrate and connected to said first source / drain region; An insulating film covering an upper surface of said word line and said bit line and having a substantially flat upper surface, said one capacitor comprising: a lower capacitor electrode formed substantially flat on the upper surface of said insulating film; Means for extending through said insulating film to connect said lower capacitor electrode to said second source / drain region; A ferroelectric film formed substantially flat on the upper surface of the lower capacitor electrode; An upper capacitor electrode formed substantially flat on an upper surface of the ferroelectric film, wherein the lower capacitor electrode, the ferroelectric film, and the upper capacitor electrode (i) each of the first and second source / drain regions; (Ii) extends over at least a portion of the gate electrode and (i) the bit line.

In this memory cell, the ferroelectric film contains Pb (Tix Zrl-x) O ₃ .

In this memory cell, the means for connection includes an electrical connection between the lower capacitor electrode and the second source / drain region, wherein the electrical connection is through the contact hole extending through the insulating film surface. It includes a conductive layer penetrating through.

In this memory cell, the conductive layer contains tungsten.

In this memory cell, another insulating film formed on the upper capacitor electrode and a conductive layer formed on the other insulating film and connected to the upper capacitor electrode via a contact hole extending through the other insulating film are added.

In this memory cell, the conductive layer comprises polysilicon.

In this memory cell, a barrier metal layer disposed between the conductive layer and the upper capacitor electrode is added.

In this memory cell, the barrier metal layer is formed from a group of materials including TiN and TiW.

In this memory cell, the one capacitor electrode is formed from a group of materials including platinum, tantalum and tungsten.

According to another aspect of the present invention, a semiconductor integrated circuit structure including at least one field effect transistor and one capacitor includes: a semiconductor substrate; Source / drain regions formed on the main surface of the semiconductor substrate, the source / drain regions being spaced apart from each other so that channel regions are formed between the source / drain regions; A gate insulating film formed over said channel region; A gate electrode formed on the gate insulating film; A bit line formed on the main surface of the semiconductor substrate and connected to one of the source / drain regions; An insulating film covering the gate electrode and the upper surface of the bit line and having a substantially flat upper surface, wherein the one capacitor comprises: a lower capacitor electrode formed substantially flat on the upper surface of the insulating film; A ferroelectric film formed substantially flat on the upper surface of the lower capacitor electrode; An upper capacitor electrode formed substantially flat on an upper surface of the ferroelectric film, wherein the lower capacitor electrode, the ferroelectric film and the upper capacitor electrode are (i) each of the source / drain regions, and (ii) the gate. And (i) extend at least a portion of the bit line.

In this circuit structure, the ferroelectric film contains Pb (Tix Zrl-x) O ₃ .

In this circuit structure, the electrical connection between the lower capacitor electrode and one of the source / drain regions includes a conductive layer penetrating the surface of the substrate via a contact hole extending through the insulating film.

In this circuit structure, the conductive layer includes tungsten or polysilicon.

In this circuit structure, another insulating film formed on the upper capacitor electrode; And a wiring layer formed on the other insulating film and connected to the upper capacitor electrode via a contact hole extending through the other insulating film.

According to another aspect of the invention, a semiconductor memory cell array of wiring in which each memory cell has one field effect transistor and one capacitor comprises: a semiconductor substrate; First and second source / drain regions formed on a major surface of the semiconductor substrate, the first and second source / drain regions being spaced apart from each other so as to form a channel region between the first and second source / drain regions; A gate insulating film formed over the channel region; A gate electrode formed over said channel region via said gate insulating film and formed by a portion of a word line; A bit line formed on a main surface of said semiconductor substrate and connected to said first source / drain region; An insulating film covering an upper surface of said word line and said bit line and having a substantially flat upper surface, wherein said one capacitor comprises: a lower capacitor electrode formed substantially flat on an upper surface of said insulating film; Means for extending through said insulating film to connect said lower capacitor electrode to said second source / drain region; A ferroelectric film formed substantially flat on the upper surface of the lower capacitor electrode; An upper capacitor electrode formed substantially flat on an upper surface of the ferroelectric film, wherein the lower capacitor electrode, the ferroelectric film, and the upper capacitor electrode comprise (i) each of the first and second source / drain regions; And (ii) the gate electrode and (iii) at least a portion of the bit line.

In this array, capacitors of adjacent memory cells extend to overlap a common bit line.

According to still another aspect of the present invention, a semiconductor memory device includes a gate formed on a part of a word line by a first and second source / drain regions formed on a main surface and a gate insulating layer on the main surface. A field effect transistor of a memory cell having an electrode; A bit line formed on said major surface and connected to said first source / drain region; An insulating film covering an upper surface of said word line and said bit line and having a substantially flat surface; A capacitor of the memory cell, the capacitor being formed substantially flat on the upper surface of the insulating film, connected to the second source / drain region, and (i) the second source / drain region And (ii) a lower electrode extending over at least a portion of said gate electrode and (iii) said bit line of said transistor; A ferroelectric film formed substantially flat on the upper surface of the lower electrode; And an upper electrode formed substantially flat on the upper surface of the ferroelectric film.

In this apparatus, the ferroelectric film includes Pb (Tix Zrl-x) O ₃ .

In this device, the connection between the lower electrode and the second source / drain region includes a conductive layer penetrating to the main surface of the semiconductor memory device via a contact hole extending through the insulating film.

In this apparatus, the electrical connection between the lower capacitor electrode and the second source / drain region is only in the contact hole by etching the applied polysilicon layer to sufficiently fill the contact hole through the insulating film through the substrate. It is formed by leaving the polysilicon layer.

A device comprising: another insulating film formed on the upper capacitor electrode; A conductive layer formed on the other insulating film, but connected to the upper capacitor electrode via a contact hole extending through the other insulating film, is added.

In this device, the conductive layer comprises polysilicon.

In this apparatus, a barrier metal layer disposed between the conductive layer and the upper capacitor electrode is added.

In this device, the barrier metal layer is formed from a group of materials including TiN and TiW.

In this device, the capacitor electrode is formed from a group of materials including platinum, tantalum and tungsten.

In the one-transistor, one-capacitor-type semiconductor memory cell according to the present invention, the capacitor including the ferroelectric film is formed on the interlayer insulating film covering the word line and the bit line and having a substantially flat surface. Membrane can be installed.

EXAMPLE

1A to 1J are schematic cross-sectional views for explaining a manufacturing process of a ferroelectric memory cell according to one embodiment of the present invention.

Referring to FIG. 1A, a field oxide film 22 and a gate insulating film 23 for separation are formed on the semiconductor substrate 21 of silicon by thermal oxidation methods.

On the gate insulating film 23, a polysilicon layer containing an impurity is deposited by the LPCVD method so as to have conductivity, and an insulating film such as a silicon oxide film is deposited by the CVD method on the polysilicon layer. These polysilicon layers and the insulating film are patterned by photolithography, and a gate electrode 24 whose upper surface is covered with the insulating film 26 is formed.

The gate electrode 24 may be formed of a polyside such as WSi ₂ , MoSi ₂ , TiSi ₂ , or a high melting point metal such as W, Mo, Ti or the like instead of polysilicon.

Referring to FIG. 1B, the sidewall of the gate electrode 24 is covered with the insulating film 26a to fit itself by anisotropically etching the deposited silicon oxide film again from above.

Referring to FIG. 1C, while the gate electrode 24 and the field oxide film 22 are used as masks, impurities are ion implanted, and the source / drain regions 25 themselves are thermally diffused by the impurities implanted therein. It fits snugly.

Referring to FIG. 1D, a contact hole 25a is drilled by photolithography to enable electrical connection to one of the source / drain regions 25. As shown in FIG.

Thereafter, a bit line 31 connected to one of the source / drain regions with a contact hole 25a interposed therebetween is formed.

The bit line 31 is formed on the bottom of the contact hole 25a, for example, a barrier metal layer such as polysilicon, polyside, TiW, TiN, or the like, and then has a high melting point such as W, Ti, Mo, or the like. It is formed by depositing a conductive layer of metal and patterning it by photolithography.

Referring to FIG. 1E, an interlayer insulating film 30 is deposited covering the bit line 31.

The deposited interlayer insulating film 30 has an upper surface substantially flat by a reflow or etch-back method.

Referring to FIG. 1f, another contact hole 25b penetrating through the interlayer insulating film 30 is opened by photolithography to enable one electrical connection to the other of the source / drain regions 25. Lose.

Referring to FIG. 1G, the contact hole 25b is buried by the wiring layer 32.

The wiring layer 32 is formed by selectively depositing a tungsten layer on the silicon substrate exposed in the contact hole 25b. (The tungsten layer can be preferentially grown on the silicon crystal.)

Alternatively, the wiring layer 32 may be left in the contact hole 25b by etching back the tungsten layer or the polysilicon layer deposited by the CVD method.

Referring to FIG. 1H, a lower capacitor electrode layer such as platinum, vanadium, tantalum or tungsten is deposited on the interlayer insulating film 30, and a ferroelectric layer is deposited thereon.

The upper capacitor electrode layer is deposited on the ferroelectric layer like the lower capacitor electrode layer.

These lower capacitor electrode layers, ferroelectric layers and upper capacitor electrode layers are patterned by photolithography, whereby a capacitor including a lower capacitor electrode 27, a ferroelectric film 28, and an upper capacitor electrode 29 is formed.

The lower capacitor electrode 27 is connected to one of the source / drain regions 25 with the wiring layer 32 therebetween.

Referring to FIG. 1I, the capacitors 27, 28, and 29 are covered by another interlayer insulating film 33, and the interlayer insulating film 33 allows electrical connection to the upper capacitor electrode 29. The contact hole 29a is drilled.

Referring to FIG. 1J, for example, an aluminum, tungsten, tungsten silicide or equivalent conductive layer is deposited so as to cover the interlayer insulating film 33 and the contact hole 29a and patterned by photolithography. 34) is formed.

At this time, a barrier metal layer such as TiN or TiW may be provided between the wiring layer 34 and the upper capacitor electrode 29.

Again, a surface protective film may be formed on the wiring layer 34, and a multilayer wiring structure may be formed again instead.

Referring to FIG. 2, the top pattern of the ferroelectric memory cell of FIG. 1j is shown.

FIG. 1J corresponds to a cross sectional view along the line 1J-1J in FIG. 2.

As described above, according to the present invention, a capacitor is formed on the interlayer insulating film 30 covering the word line 24 or the bit line 31 and having a substantially flat upper surface.

Therefore, the capacitor can be formed wide without being limited by the position of the word line 24 or the bit line 31, and the ferroelectric film 28 in the capacitor is formed flat.

As a result, the capacity of the capacitor per memory cell can be increased, and fatigue breakdown of the ferroelectric film 28 can be prevented.

Although the invention has been described in detail, it is to be clearly understood that the spirit or scope of the invention is not limited by the same and by way of example only the terms of the appended claims.

Claims (16)

The semiconductor substrate 21, the source / drain region 25 formed on the main surface of the semiconductor substrate 21 opposite to the channel region, and the gate insulating layer 23 formed on the channel region. A bit line 31 formed on a word line 24, an insulating layer 26 on the main surface and electrically connected to one of the source / drain regions 25, and the word line ( An interlayer insulating film 30 covering the bit line 31 and the bit line 31 and having a substantially flat upper surface, and formed on the interlayer insulating film 30 substantially flat, and having a source / drain region ( A semiconductor memory cell having a field effect transistor and a capacitor including a lower capacitor electrode 27 electrically connected to the other of 25, wherein the ferroelectric layer 28 is substantially flat on the lower capacitor electrode 27. ) Is formed, and An upper capacitor electrode 29 is formed on the ferroelectric layer 28, and the lower capacitor electrode 27, the ferroelectric layer 28, and the upper capacitor electrode 29 are at least the word line 24 and the bit line 31. And a field effect transistor and a capacitor, wherein the semiconductor memory cell is formed so as to cover a part of the circuit. The semiconductor memory cell of claim 1, wherein the ferroelectric layer (28) contains Pb (Ti _X Zr _1-X ) O ₃ . The semiconductor memory cell according to claim 1 or 2, wherein an upper surface of said interlayer insulating film (30) is flattened by a reflow method. The semiconductor memory cell according to claim 1 or 2, wherein an upper surface of said interlayer insulating film (30) is flattened by an etch-back method. 3. The tungsten according to claim 1 or 2, wherein the semiconductor substrate 21 contains silicon, and tungsten is selectively deposited on the surface of the silicon substrate in the contact hole 25a penetrating through the interlayer insulating film 30. And the lower capacitor electrode (27) and the source / drain region (25) are electrically connected by a layer. The lower capacitor electrode 27 and the lower electrode of claim 1 or 2, wherein the lower capacitor electrode 27 is formed by a polysilicon layer sufficiently deposited in the contact hole 25b that penetrates the interlayer insulating film 30 up to the substrate and then etched back. A semiconductor memory cell, characterized in that between source / drain regions 25 is electrically connected. The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and the wiring layer 34 is formed on the second interlayer insulating film 33. And an upper capacitor electrode (29) connected through a contact hole (29a) in said second interlayer insulating film (33). 4. The semiconductor substrate (21) according to claim 3, wherein the semiconductor substrate (21) contains silicon and is formed by a tungsten layer selectively deposited on the surface of the silicon substrate in a contact hole (25a) penetrating through the interlayer insulating film (30). And a lower capacitor electrode (27) and a source / drain region (25) electrically connected to each other. 5. The semiconductor substrate 21 according to claim 4, wherein the semiconductor substrate 21 contains silicon and is formed by a tungsten layer selectively deposited on the surface of the silicon substrate in the contact hole 25a penetrating through the interlayer insulating film 30. And a lower capacitor electrode (27) and a source / drain region (25) electrically connected to each other. 4. The lower capacitor electrode 27 and the source / drain region (4) according to claim 3, wherein the lower capacitor electrode (27) and the source / drain region are formed by a polysilicon layer sufficiently deposited in the contact hole 25b penetrating the interlayer insulating film 30 up to the substrate and 25) A semiconductor memory cell, characterized in that electrically connected between. The lower capacitor electrode 27 and the source / drain region of claim 4 are formed by a polysilicon layer sufficiently deposited and then etched back into the contact hole 25b penetrating the interlayer insulating film 30 up to the substrate. A semiconductor memory cell, characterized in that electrically connected between (25). 4. The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and a wiring layer 34 formed on the second interlayer insulating film 33 is formed between the second interlayers. A semiconductor memory device characterized in that it is connected to the upper capacitor electrode (29) through a contact hole (29a) in the insulating film (33). 5. The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and the wiring layer 34 formed on the second interlayer insulating film 33 is formed between the second interlayers. A semiconductor memory device characterized in that it is connected to the upper capacitor electrode (29) through a contact hole (29a) in the insulating film (33). 6. The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and the wiring layer 34 formed on the second interlayer insulating film 33 is formed between the second interlayers. A semiconductor memory device characterized in that it is connected to the upper capacitor electrode (29) through a contact hole (29a) in the insulating film (33). The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and the wiring layer 34 formed on the second interlayer insulating film 33 is formed between the second interlayers. A semiconductor memory device characterized in that it is connected to the upper capacitor electrode (29) through a contact hole (29a) in the insulating film (33). 12. The second interlayer insulating film 33 is formed on the upper capacitor electrode 29, and is formed on the second interlayer insulating film 33. And a wiring layer (34) connected to the upper capacitor electrode (29) through a contact hole (29a) in the second interlayer insulating film (33).

Images