KR950005095A - Sound source delay circuit using memory - Google Patents
Sound source delay circuit using memory Download PDFInfo
- Publication number
- KR950005095A KR950005095A KR1019930013384A KR930013384A KR950005095A KR 950005095 A KR950005095 A KR 950005095A KR 1019930013384 A KR1019930013384 A KR 1019930013384A KR 930013384 A KR930013384 A KR 930013384A KR 950005095 A KR950005095 A KR 950005095A
- Authority
- KR
- South Korea
- Prior art keywords
- sound source
- output
- speaker
- speakers
- memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R3/00—Circuits for transducers, loudspeakers or microphones
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S7/00—Indicating arrangements; Control arrangements, e.g. balance control
- H04S7/30—Control circuits for electronic adaptation of the sound field
- H04S7/302—Electronic adaptation of stereophonic sound system to listener position or orientation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Reverberation, Karaoke And Other Acoustics (AREA)
- Circuit For Audible Band Transducer (AREA)
Abstract
본 발명은 음원 지연 회로에 관한 것으로, 더욱 상세하게는 다수의 스피커로 하나의 스피커로 하나의 음원을 출력시킬 때 메모리를 이용하여 일부 스피커로 출력하는 음원을 지연시켜 출력하여 음원과 스피커와의 거리에 관계없이 모든 스피커에서 음원이 동시에 출력되도록 하는 메모리를 이용한 지연회로에 관한 것이다.The present invention relates to a sound source delay circuit, and more particularly, when a single sound source is output to one speaker by a plurality of speakers, a distance between the sound source and the speaker by delaying and outputting the sound source output to some speakers by using a memory. The present invention relates to a delay circuit using a memory so that a sound source can be simultaneously output from all speakers regardless.
즉 다수의 스피커로부터 출력되는 음원의 출력시간을 임의로 지연시켜 출력함으로서 음원 청취위치와 관계없이 청취자는 모든 위치에서 스피커에서 출력되는 음원을 동시에 청취할 수 있도록 한 메모리를 이용한 음원 지연 회로에 관한 것이다.That is, the present invention relates to a sound source delay circuit using a memory that allows a listener to simultaneously listen to a sound source output from a speaker at all positions regardless of a sound source listening position by randomly delaying and outputting the output time of sound sources output from a plurality of speakers.
종래 하나의 음원 발생부로부터 출력된 음원을 다수의 스피커로 출력함에 있어서는 모든 스피커에 대하여 동일한 시간에 음원을 출력하도록 구성되어져 음원 발생부와 스피커간에 대칭관계에 의하여 각 스피커마다 서로 다른 시각에 음원이 출력되어지는 경우가 있었다.Conventionally, in outputting a sound source output from a single sound source generator to a plurality of speakers, the sound source is configured to output all the speakers at the same time to all the speakers. It might be printed.
즉 음원 발생부로부터 가까운 곳에 설치된 스피커에서는 음원이 빨리 출력되어지는 반면에 음원으로부터 먼 곳에 설치되어진 스피커로부터는 음원이 뒤늦게 출력되어져 이를 듣는 사람은 메아리를 듣는 것과 같이 음원이 이중으로 들려 정확한 음원을 들을 수 없었다.That is, the sound source is outputted quickly from the speaker installed close to the sound source generator, while the sound source is output late from the speaker installed far from the sound source, and the listener hears the sound as if they hear the echo and hear the correct sound source. Could not.
또한 대중을 가운데 두고 스피커를 설치하였을 경우에는 스피커마다 각기 다른 시각에 음원을 출력함으로 대중들은 음원을 정확하게 듣지 못하는 불편함이 있었다.In addition, when the speaker was installed in the middle of the public, the speakers output the sound at different times, so that the public could not hear the sound source accurately.
따라서 본 발명 메모리를 이용한 음원 지연회로는 제 1 도에서와 같이 음원 발생부로부터 발생한 음원 신간 지연없이 스피커로 출력시켜 스피커로 출력함으로서 청취자는 장소에 관계없이 다수의 스피커 출력을 동시에 들을 수 있는 효과가 있다.Therefore, the sound source delay circuit using the memory of the present invention outputs the speaker to the speaker without delay of the sound source new signal generated from the sound source generator as shown in FIG. 1 so that the listener can simultaneously listen to the output of multiple speakers regardless of the location. have.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 1 도는 본 발명에 따른 블록도.1 is a block diagram according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930013384A KR960012985B1 (en) | 1993-07-15 | 1993-07-15 | Source delay circuit using memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930013384A KR960012985B1 (en) | 1993-07-15 | 1993-07-15 | Source delay circuit using memory |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950005095A true KR950005095A (en) | 1995-02-18 |
KR960012985B1 KR960012985B1 (en) | 1996-09-25 |
Family
ID=19359360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930013384A KR960012985B1 (en) | 1993-07-15 | 1993-07-15 | Source delay circuit using memory |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960012985B1 (en) |
-
1993
- 1993-07-15 KR KR1019930013384A patent/KR960012985B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960012985B1 (en) | 1996-09-25 |
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GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19990831 Year of fee payment: 4 |
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LAPS | Lapse due to unpaid annual fee |