KR950004558A - Semiconductor Memory Structure and Semiconductor Manufacturing Method - Google Patents

Semiconductor Memory Structure and Semiconductor Manufacturing Method Download PDF

Info

Publication number
KR950004558A
KR950004558A KR1019930013469A KR930013469A KR950004558A KR 950004558 A KR950004558 A KR 950004558A KR 1019930013469 A KR1019930013469 A KR 1019930013469A KR 930013469 A KR930013469 A KR 930013469A KR 950004558 A KR950004558 A KR 950004558A
Authority
KR
South Korea
Prior art keywords
transistors
melting point
forming
high melting
point metal
Prior art date
Application number
KR1019930013469A
Other languages
Korean (ko)
Inventor
이태정
신헌종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930013469A priority Critical patent/KR950004558A/en
Publication of KR950004558A publication Critical patent/KR950004558A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Abstract

2개의 구동 트랜지스터, 2개의 전송 트랜지스터 및 2개의 부하를 포함하여 구성되는 SRAM 메모리셀에서 부하의 저항값을 높게 하기 위하여, 부하를 저항과 숏트키 다이오드를 포함하여 구성한다. 여기서 숏트키 다이오드는 저항과 구동 트랜지스터의 드레인 사이에 역방향으로 결합되어 흐르는 전류가 작게 된다. 이와 같은 메모리 셀 회로를 구현하기 위한 반도체 장치는 제 1 전원전압(VDD)이 인가되는 제 1 전원라인을 제 2 금속층으로 형성하고, 저항들을 불순물이 도핑되지 않는 폴리실리콘층으로 형성하며, 저항들과 각 구동 트랜지스터들의 드레인을 접속시키기 위한 배선층들 또한 금속층으로 형성한다. 그리하여 저항들의 양측 접합면들에는 상호 대향하고 있는 숏트키 다이오드들이 형성되게 되어 저항값이 높아지게 되고 그에 따라 전류소비가 줄어드는 잇점이 있게 된다.In an SRAM memory cell including two driving transistors, two transfer transistors, and two loads, the load is configured to include a resistor and a Schottky diode to increase the resistance of the load. Here, the Schottky diode has a small current flowing in the reverse direction between the resistor and the drain of the driving transistor. In the semiconductor device for implementing such a memory cell circuit, the first power line to which the first power voltage VDD is applied is formed of a second metal layer, and the resistors are formed of a polysilicon layer that is not doped with impurities. And wiring layers for connecting the drains of the respective driving transistors to the metal layer. Thus, opposing Schottky diodes are formed on both junctions of the resistors, thereby increasing the resistance value and thus reducing the current consumption.

Description

반도체 메모리 구조 및 반도체 제조방법Semiconductor Memory Structure and Semiconductor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 4 도는 본 발명의 실시예에 따른 SRAM메모리셀의 회로도, 제5A도 및 제5B도는 본 발명의 실시예에 따른 반도체 장치 및 제조방법을 설명하기 위한 평면도들.4 is a circuit diagram of an SRAM memory cell according to an embodiment of the present invention, FIGS. 5A and 5B are plan views illustrating a semiconductor device and a manufacturing method according to an embodiment of the present invention.

Claims (4)

반도체 기판상에 2개의 구동 트랜지스터와 2개의 전송트랜지스터가 2개의 저항과 연결되어 메모리셀을 이루고 있는 스태틱 램 구조에 있어서, 상기 반도체 기판위에 형성된 복수의 구동 및 전송 트랜지스터들; 상기 기판위에 소정 절연층을 개재하여 그 위에 형성된 저항용 비불순물 폴리실리콘층; 및 상기 구동, 전송 트랜지스터와 각 저항을 연결하기 위하여 고융점 금속으로 형성되는 배선층을 구비하는 것을 특징으로 하는 반도체 메모리 구조.A static RAM structure in which two driving transistors and two transfer transistors are connected to two resistors on a semiconductor substrate to form a memory cell, comprising: a plurality of driving and transfer transistors formed on the semiconductor substrate; An impurity-free polysilicon layer formed over the substrate via a predetermined insulating layer thereon; And a wiring layer formed of a high melting point metal to connect the driving and transfer transistors to respective resistors. 제 1 항에 있어서, 고융점 금속으로 형성된 배선층과 폴리실리콘층의 접속 부위에 숏트키 다이오드가 형성되는 것을 특징으로 하는 반도체 메모리 구조.The semiconductor memory structure according to claim 1, wherein a Schottky diode is formed at a connection portion between the wiring layer formed of the high melting point metal and the polysilicon layer. 반도체 기판상에 2개의 구동트랜지스터와 2개의 전송트랜지스터와 2개의 저항이 연결되어 메모리 셀을 이루는 스태틱 램 제조방법에 있어서, 상기 반도체 기판위에 다수개의 트랜지스터를 형성하는 공정; 상기 기판 및 상기 트랜지스터상에 층간 절연막을 형성하는 공정; 상기 층간 절연막이 소정부위에 콘택홀을 형성하는 공정; 상기 콘택홀과 층간절연막상에 고융점 금속으로 배선층을 형성하는 공정; 및 상기 절연막상에 상기 고융점금속으로 형성된 배선층과 연결되면서 저항으로 사용되는 비불순물 폴리실리콘층을 형성하는 공정을 구비하는 것을 특징으로 하는 반도체 제조방법.A method of manufacturing a static RAM comprising two driving transistors, two transfer transistors, and two resistors on a semiconductor substrate, the memory cell comprising: forming a plurality of transistors on the semiconductor substrate; Forming an interlayer insulating film on the substrate and the transistor; Forming a contact hole in a predetermined portion of the interlayer insulating film; Forming a wiring layer of a high melting point metal on the contact hole and the interlayer insulating film; And forming an impurity polysilicon layer used as a resistance while being connected to the wiring layer formed of the high melting point metal on the insulating film. 제 3 항에 있어서, 상기 고융점 금속은 실리콘과의 일함수에 차이에 의하여 숏트키 현상이 현저하게 되는 텅스턴이나 티타늄중 그 하나인 것을 특징으로 하는 반도체 제조방법.4. The semiconductor manufacturing method according to claim 3, wherein the high melting point metal is one of tungsten or titanium in which a Schottky phenomenon is remarkable due to a difference in work function with silicon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930013469A 1993-07-16 1993-07-16 Semiconductor Memory Structure and Semiconductor Manufacturing Method KR950004558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930013469A KR950004558A (en) 1993-07-16 1993-07-16 Semiconductor Memory Structure and Semiconductor Manufacturing Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930013469A KR950004558A (en) 1993-07-16 1993-07-16 Semiconductor Memory Structure and Semiconductor Manufacturing Method

Publications (1)

Publication Number Publication Date
KR950004558A true KR950004558A (en) 1995-02-18

Family

ID=67143041

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930013469A KR950004558A (en) 1993-07-16 1993-07-16 Semiconductor Memory Structure and Semiconductor Manufacturing Method

Country Status (1)

Country Link
KR (1) KR950004558A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100893475B1 (en) * 2001-11-16 2009-04-17 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 Sense amplifier with independent write-back capability for ferroelectric random-access memories

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100893475B1 (en) * 2001-11-16 2009-04-17 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 Sense amplifier with independent write-back capability for ferroelectric random-access memories

Similar Documents

Publication Publication Date Title
EP0836194B1 (en) Semiconductor device
KR940004830A (en) Semiconductor integrated circuit device
KR890013777A (en) Semiconductor integrated circuit device and manufacturing method thereof
KR900004039A (en) Composite MOS transistors and their applications as freewheel diodes
US6639326B2 (en) Full CMOS SRAM cell
JPS6164166A (en) Semiconductor device
US4799101A (en) Substrate bias through polysilicon line
KR920018943A (en) Semiconductor memory
KR940010348A (en) Semiconductor memory device and manufacturing method thereof
KR910010741A (en) Semiconductor integrated circuit device
KR960009161A (en) Semiconductor integrated circuit
KR950021462A (en) Semiconductor integrated device having a temperature detection circuit and its operating method
KR950021672A (en) Static RAM with Thin Film Transistors Acting as Load
US4504743A (en) Semiconductor resistor element
KR900008658A (en) Semiconductor devices
JP2743376B2 (en) Manufacturing method of thin film integrated circuit
US6121657A (en) Semiconductor integrated circuit device having gates arranged in a lattice
US6580592B2 (en) Semiconductor device
KR950004558A (en) Semiconductor Memory Structure and Semiconductor Manufacturing Method
KR0130777B1 (en) Semiconductor integrated circuit device
KR970077679A (en) High resistance load type static RAM cell and method of manufacturing the same
US5241204A (en) Semiconductor memory
JPS6233752B2 (en)
US5452247A (en) Three-dimensional static random access memory device for avoiding disconnection among transistors of each memory cell
KR890005879A (en) Static Memory Using Schottky Technology

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid