KR950003009B1 - Electronic alarm watch - Google Patents

Abstract

No content.

Description

Electronic clock with alarm

1 is an IC block diagram showing an embodiment of the electronic clock with alarm of the present invention.

FIG. 2 is a block diagram showing a concrete configuration example of the chronograph circuit 211 of FIG.

3 is a block diagram showing a concrete configuration example of the motor driving control circuit 212 of FIG.

FIG. 4 is a diagram showing an example of the specific configuration of the moving reference signal forming circuit 220 of FIG.

5, 6, 7, and 8 illustrate the first driving pulse forming circuit 221, the second driving pulse forming circuit 222, the third driving pulse circuit 223, and the fourth drawing of FIG. 1, respectively. Timing diagram of motor drive pulses Pa, Pb, Pc, and Pd output from the drive pulse shaping circuit 224. FIG.

9 is a block diagram showing a concrete configuration example of the motor clock control circuits 226, 227, 228, and 229 in FIG.

10 is a plan view showing one embodiment of an analog electronic clock of the present invention.

11 is a cross-sectional view of a normal heat time minute display.

12 is a cross-sectional view of a leap heat for displaying normal seconds.

13 is a cross-sectional view of the chromograph second display wheel heat.

14 is a cross-sectional view of the wheel heat for chronograph minute display and timer second display.

Fig. 15 is a sectional view of the wheel heat for alarm setting time display.

FIG. 16 is a circuit connection diagram of the embodiment of FIG.

17 is an external view of a complete body of the multifunction electronic clock of this embodiment.

18A and 18B are flowcharts for displaying normal time.

19a and 19b are flowcharts of the chronograph function.

20a and 20b are flow charts of a timer function.

21a and 21b are flowcharts of the alarm function.

2A, 22B and 22C are flowcharts of a method of driving a motor.

FIG. 23 shows digital display means as an additional part to the first embodiment of the second embodiment; FIG.

* Explanation of symbols for main parts of the drawings

2: battery 3: stepper motor A

4: rotor 5: 5th wheel

6: 6th wheel 7: 3rd wheel

8: wheel 2 9: the fast wheel of the date

10: wheel 15: stepper motor B

16: rotor 17: 1/5 second hand CG middle wheel

18: 1/5 second CG middle wheel 19: 1/5 second CG wheel

27: step motor C 28: rotor

29: Minute CG Wheels 30: Minute CG Wheels

32: step motor D 33: rotor

34: AL middle wheel 35: AL minute wheel

36: wheel of AL date 37: AL wheel

201: core CPU 202: program memory

204: data memory 211: chronograph circuit

212: motor drive control circuit 213 to 216: motor driver

217: input control and reset signal forming circuit

218: interrupt control circuit 219: motor driving method control circuit

210: moving reference signal forming circuit

221 to 225: motor drive pulse shaping circuit

226 to 229: motor clock control circuit 230 to 233: trigger shaping circuit

234 to 237: Motor Driven Pulse Selection Circuit

Industrial use

The present invention relates to an alarm function of an electronic clock with alarm.

Conventional technology

The conventional analog display electronic clock with alarm has an alarm ringing mode and an alarm ringing mode.In the alarm ringing mode, the alarm set time is maintained even after the alarm ringing, and a predetermined time passes after the alarm ringing, and the alarm set time and present time are again present. The alarm sounded even when this match was made.

Problems to be Solved by the Invention

However, in the conventional analog display electronic clock with alarm, if you do not want to sound the alarm again after alarm, you should not prohibit the alarm by the switch operation, and when you set the alarm again in the prohibition state of the alarm The operation was complicated because the prohibition state of the alarm sound had to be released.

In addition, for example, in the case of using the summer-time operation method to sound an alarm after 10 minutes, the user needs to calculate the time added by 10 minutes to the current time, and the operation of adjusting the alarm set time to that time is complicated. It was necessary.

Therefore, the present invention is to eliminate such a problem, the purpose of the operation is to stop the alarm ringing when you do not want to sound the alarm again after the alarm ringing, and to cancel the operation of the alarm ringing inhibited state when the alarm is set again To simplify the operation, reduce the external operation member, increase the multifunction of the alarm function, and simplify the timer-based method of using the alarm function.

Means for Solving the Invention

The electronic clock with alarm of the present invention has a plurality of step motors, display instructions driven by the same step motor, external operation means, alarm ringing means and alarm control means. The display instructions display the current time in the alarm non-set state, the display instructions displaying the current time display the alarm set time during and after the alarm set, and become the alarm non-set state after the alarm sounds, The display instruction may display the current time again.

Action

According to the above configuration of the present invention, by the alarm control means and the step motor, one or more sets of display instructions display the current time in the alarm non-set state, and the display instructions for displaying the current time are set during the alarm set and the alarm. After the set, the alarm set time is displayed. After the alarm is sounded, the alarm set time is not set, and the display instruction displays the current time again.

If the alarm set time and current time coincide with each other by the alarm control means, the alarm set time and current time coincide with each other, and the alarm set time and current time coincide with the alarm set time. The alarm set time stops at the set time.

Example

1 is a block diagram showing an IC of an embodiment of the electronic clock with alarm of the present invention.

As shown in FIG. 1, the CMOS-IC 20 is an IC in which a program memory, a data memory, four motor drivers, a motor driving control circuit, a sound generator, an interrupt control circuit, etc. are integrated on a single chip centered on a core CPU. One-chip microcomputer for log electronic clock.

1 will be described below.

Reference numeral 201 denotes a core CPU, and is composed of an ALU operation register, an address control register, a stack pointer instruction register, an instruction decoder, and the like. The peripheral circuit is connected to an address bus (adbus) by a memory mapped I / O method. It is connected to a data bus (dbus).

Reference numeral 202 denotes a program memory consisting of a mask ROM having a 2048 word x 12-bit configuration, and contains software for operating the IC.

Reference numeral 202 denotes a program memory consisting of a mask ROM having a 2048 word x 12-bit configuration, and contains software for operating the IC.

203 is an address decoder of the program memory 202.

Reference numeral 204 denotes a data memory composed of a RAM of 112 words x 4 bits, and is used for a timer for various clocks, a count for storing the needle position of each instruction, and the like.

205 is an address decoder of the data memory 204.

Numeral 206 denotes an oscillation circuit, which oscillates at 32,768 Hz in a circle with a tuning fork crystal oscillator connected to the Xin and Xout terminals.

Numeral 207 is an oscillation stop detection circuit. When oscillation of the oscillation circuit 206 stops, it detects it and resets the system.

32K)를 순차 분주하여 16Hz신호(

16)를 출력한다.Reference numeral 208 denotes a first division circuit, and a 32,768 Hz signal (outputted from the oscillator circuit 206)

Sequentially divide 32K) into 16Hz

Output 16).

16)를 1Hz신호(

1)까지 분주한다. 또, 8Hz에서 1Hz까지의 각 분주단의 상태는 소프트웨어에 의하여 코아 CPU(201)내로 읽어들일 수 있다.Reference numeral 209 denotes a second divider circuit, and a 16 Hz signal (outputted from the first divider circuit 208 (

16) to 1 Hz signal (

Busy until 1). In addition, the state of each frequency division stage from 8 Hz to 1 Hz can be read into the core CPU 201 by software.

16) 8Hz신호(

8), 1Hz신호(

1)를 사용하고 있다. 타임 인터럽트(Tint)는 각신호의 하강에서 발생하고, 각 인터럽트 요인의 읽어넣기와 리셋트 및 마스크는 모두 소프트웨어에 의하여 행해지며, 리셋트와 마스크에 대하여는 각 요인마다 개별로 행하도록 구성되어 있다.In the IC of the present embodiment, a 16 Hz signal (as a time interrupt Tint for processing clocks and the like) is used.

16) 8 Hz signal (

8), 1 Hz signal (

1) is used. The time interrupt Tint occurs at the fall of each signal, and reading, resetting, and masking of each interrupt factor are performed by software, and the reset and mask are configured to be performed individually for each factor.

Reference numeral 210 is an acoustic generator, which forms a buzzer driving signal and outputs it to the AL terminal. The drive frequency, ON / OFF, and ringing pattern of the buzzer drive signal can be controlled by software.

Denoted at 211 is a chronograph circuit, specifically, as shown in FIG. 2, and when configuring a 1/100 second chronograph, the load of software that performs a 1/100 second hand movement control as hardware is remarkably reduced. It is possible.

512)로부터 크로노그래프 계측의 기준 클럭으로 되는 100Hz신호(

100)와, 1/00초침 구동 펄스(Pf)를 형성하기 위한 100Hz로 펄스폭 3.91ms의 클럭 펄스(Pfc)를 형성한다. (2112)는 50진의 크로노그래프 카운터이고, AND게이트(2119)를 통과하는

100을 카운트하고, 제어 신호 형성 회로(2118)에서 출력되는 크로노그래프 리셋트 신호 Rcg로 리셋트된다. (2113)은 레지스터이고, 제어 신호 형성 회로(2118)에서 스플릿 표시 지령 신호(SP)가 출력되었을 때에 크로노그래프카운터(2112)의 내용을 홀드한다. (2114)는 50진의 침 위치 카운터이고, 1/110초침 구동 펄스(Pf)를 카운트함으로써 1/110초침의 표시 위치를 기억하고, 제어 신호 형성 회로(2118)로부터 1/100초침의 위치를 기억시키기 위한 신호의 Rhnd에 의하여 리셋트된다. (2115)는 일치 검출 회로이고, 레지스터(2113)와 침 위치 카운터(2114)의 내용을비교하여 일치하고 있을 때에는 일치 신호(Dty)를 출력한다. (2116)은 0위치 검출 회로이며, 침위치 카운터(2114)의 0을 검출하면 0검출 신호 Dt

를 출력한다. (2117)은 1/00초침 운침제어 회로이고, 1/100 초침 동작상태 게다가 크로노그래프 계측 기간중은 크로노그래프 카운터(2112)와 침위치 카운터(2114)의 내용이 일치하고 있을 때에 클럭 펄스(Pfc)를 통하고, 스플릿 표시시 및 계측 정지시에는 레지스터(2133)와 침위치 카운터(2114)가 일치하고 있지 않을 때에 클럭 펄스(Pfc)를 통하고, 1/00 초침 비동작 상태에서 크로노그래프 계측중에는 침위치 카운터(2125)의 내용이 0이외일 때에 클럭 펄스(Pfc)를 통하도록 구성되어 있다. (2118)은 제어 신호 형성 회로이고, 소프트웨어의 지령에 의하여 크로노그래프 계측의 스타트/스톱을 지령하는 스타트 신호(St), 스플릿 표시/스플릿 표시 해제를 지령하는 스플릿 신호(Sp), 크로노그래프 계측의 리셋트를 지령하는 크로노그래프 리셋트 신호(Rcg), 1/100초침의 0위치를 기억시키기 위한 0위치의 신호(Rhnd) 및 1/00초침의 동작/비동작을 지령하는 Drv를 형성하여 출력한다. 또, 1/100초침 구동은 스텝 모터 C만으로 가능하다. 또, 크로노그래프카운터(2112)에서 출력되는 5Hz의 캐리 신호(

5)에 의하여 크로노그래프 인터럽트(CGint)가 발생하고, 소프트웨어에 의하여 1/5초 이하의 크로노그래프 계측 처리가 가능하다.In FIG. 2, 2111 is a clock forming circuit, and a 512 Hz signal (

100 Hz signal from 512 to the reference clock for chronograph measurement (

100) and a clock pulse Pfc having a pulse width of 3.91 ms at 100 Hz for forming the 1/00 second hand driving pulse Pf. (2112) is a 50-degree chronograph counter that passes through AND gate 2119

100 is counted and reset to the chronograph reset signal Rcg output from the control signal forming circuit 2118. Reference numeral 2113 denotes a register that holds the contents of the chronograph counter 2112 when the split display command signal SP is output from the control signal forming circuit 2118. 2114 is a 50-digit needle position counter, which stores the display position of the 1/110 second hand by counting the 1/110 second hand drive pulse Pf, and stores the position of the 1/100 second hand from the control signal forming circuit 2118. Is reset by the Rhnd of the signal to Reference numeral 2115 denotes a coincidence detection circuit, and compares the contents of the register 2113 and the needle position counter 2114 to output a coincidence signal Dty. 2116 is a zero position detection circuit, and when zero of the needle position counter 2114 is detected, the zero detection signal Dt is detected.

Outputs Reference numeral 2117 denotes a 1/00 second hand operation control circuit, and the clock pulse Pfc when the contents of the chronograph counter 2112 and the needle position counter 2114 coincide during the 1/100 second hand operation state and the chronograph measurement period. The chronograph is measured by the clock pulse Pfc when the register 2133 and the needle position counter 2114 do not coincide at the time of split display and measurement stop. Is configured to pass through the clock pulse Pfc when the contents of the needle position counter 2125 are other than zero. Reference numeral 2118 denotes a control signal forming circuit, which includes a start signal St for commanding start / stop of chronograph measurement, a split signal Sp for commanding split display / split display release, and a chronograph measurement command. A chronograph reset signal (Rcg) for commanding reset, a signal (Rhnd) for storing the 0 position of the 1/100 second hand, and a Drv for the operation / non-operation of the 1/00 second hand are formed and output. do. In addition, 1/100 second hand drive is possible only with the step motor C. Also, a 5 Hz carry signal (outputted from the chronograph counter 2112)

5) a chronograph interrupt (CGint) is generated, and chronograph measurement processing of 1/5 seconds or less is possible by software.

Reference numeral 212 is a motor driving control circuit, specifically configured as shown in FIG. 3, and outputs motor drive pulses to each motor driver based on instructions from software. 3 will be described below.

Reference numeral 219 denotes a motor driving method control circuit, which stores the driving method of each motor according to instructions from software, selects the electrostatic drive I (Sa), selects the electrostatic drive II (Sb), and reverse drive I. Each control signal of (Sc) for selecting (Sc), (Sd) for selecting reverse driving (II) and Se for selecting electrostatic correction driving is formed and output.

Reference numeral 220 denotes a moving reference signal forming circuit, which is specifically configured similarly to FIG. 4, and forms and outputs a moving reference clock Cdrv by a command from software.

256)를 , 데코더(2204)에서 출력되는 수치를 n으로 하면, 1/n으로 분주하여 출력한다. 따라서 운침 기준 신호 형성 회로(220)는 소프트웨어로부터의 지령에 의하여 운침용 기준 클럭(Cdrv)의 주파수를 128Hz, 85.3Hz, 64Hz, 51.2Hz, 42.7Hz, 32Hz, 25.6Hz, 16Hz의 8종류로 선택할 수 있다. 또, 운침용 기준 클럭(Cdrv)의 주파수 변경은 레지스터(2203)에 데이타가 취입한 시점에서 일어나게 되며, 레지스터(2203)으로의 데이타 취입은 운침 기준요 클럭(Cdrv)에 동기하여 일어나기때문에, 전 주파수(fa)에서 다음 주파수(fb)로 절체할 때에는 반드시 1/fa의 간격이 확보된다.In Fig. 4, 2201 is a 3-bit register and stores data for determining the frequency of the driving reference clock Cdrv by a command from the software (output signal of the address decoder 2202). Reference numeral 2203 denotes a 3-bit register that takes in and stores data stored in the register 2201 at the falling of the driving reference clock Cdrv output from the programmable divider 2205. 2204 is a decoder, and outputs the number of 2, 3, 4, 5, 6, 8, 10, 16 in binary form corresponding to the data stored in the register 2203. Numeral 2205 denotes a programmable divider, and a 256 Hz signal (outputted from the first divider circuit 208).

When 256 is a numerical value output from the decoder 2204, n is divided and output as 1 / n. Therefore, the driving reference signal forming circuit 220 selects the frequency of the driving reference clock Cdrv from eight types of 128 Hz, 85.3 Hz, 64 Hz, 51.2 Hz, 42.7 Hz, 32 Hz, 25.6 Hz, and 16 Hz according to a command from the software. Can be. In addition, the frequency change of the driving reference clock Cdrv occurs at the time when data is taken into the register 2203, and the data injection into the register 2203 occurs in synchronization with the driving reference clock Cdrv. When switching from frequency fa to the next frequency fb, an interval of 1 / fa is always secured.

When the electrostatic driving I and the reversing driving are performed continuously, the frequency of the driving reference clock Cdrv is limited to 64 Hz or less.

Reference numeral 221 denotes a first drive pulse forming circuit, which forms and outputs a drive pulse Pa for the stop drive I shown in FIG.

Reference numeral 222 denotes a second drive pulse forming circuit, which forms and outputs a drive pulse Pb for the electrostatic drive II shown in FIG.

Reference numeral 223 denotes a third drive pulse forming circuit, which forms and outputs the drive pulse Pc for the reverse drive I shown in FIG.

Reference numeral 224 denotes a fourth driving pulse forming circuit, which forms and outputs the driving pulse Pd for the inversion driving II shown in FIG.

Reference numeral 225 denotes a fifth drive pulse forming circuit, and includes a pulse group Pe for correction driving (normal drive pulse P ₁ disclosed in Japanese Patent Laid-Open No. 60-260883, correction drive pulse P ₂ , and alternating current). The magnetic field detection pulse P ₃ , the AC magnetic field detection pulse Sp ₁ , and the rotation detection pulse SP ₂ are formed and output.

Reference numerals 226, 227, 228, and 229 are motor clock control circuits, and are specifically configured as shown in FIG. 9, and the number of driving pulses of the step motor A, the step motor B, the step motor C, and the step motor D, respectively, is determined from software. Control by instruction.

In Fig. 9, 2221 denotes 4 bits as a register, and stores the number of moving pulses commanded by software. 2226 is a 4-bit up counter, counts the driving reference clock Cdrv passing through the AND gate 2274, and is reset by the control signal Reset. Reference numeral 2263 denotes a coincidence detection circuit, which compares the contents of the registers 2226 and the up counter 2262 and outputs a coincidence signal Dy when they match. 2264 is an all 1 detection circuit, and outputs an all 1 detection signal D15 when the contents of the register 2226 are all 1. Reference numeral 2265 denotes a trigger signal generation circuit for forming a motor driving pulse, and includes a NOT gate 2266 and 2267, a three input AND gate 2268, a two input AND gate 2269, and a two input OR gate 2270. When all 1s are set in the register 2226, the motor pulses are continuously output until other data is set. When data other than all 1s is set, the motor pulses are output as much as the data, and the next data is The motor pulse output is configured to stop until set. 2227 is a bidirectional switch and is turned on when a control signal Sread is output, and loads data from the up counter 2262 on the data bus. 2227 is a control signal forming circuit, which is a signal Sset for setting the number of latch pulses in the register 2226 by a command from software, and a signal for reading data of the up counter 2262. A signal (Sreset) for resetting the register 2226 and the up counter 2262 is formed and output. In addition, when the signal Sread is outputted, passage of the driving reference clock Cdrv is prohibited by the NOT gate 2273 and the AND gate 2274. In this case, after reading, it is necessary to generate a signal (Sreset) to reset the register (2261) and the up counter (2262). When the coincidence detection circuit 2263 detects a coincidence (when it finishes by outputting the set number of pulses), each motor generates a motor control interrupt Mint. When a motor control interrupt occurs, the software can read which interrupt occurred and reset it after the read.

230, 231, 232, and 233 are trigger forming circuits, and triggers output from the motor clock control circuit in response to the driving method control signals Sa, Sb, Sc, Sd, and Se output from the motor driving method control circuit 219. Trigger signals Sat, Sbt, Sct, which are used to form the motor drive pulses Pa, Pb, Pc, Pd, Pe by the respective drive pulse control circuits of the signal Tr (221, 222, 223, 224, 225). Sdt, Set).

Reference numerals 234, 235, 236, and 237 are drive pulse selection circuits, and motor drive pulses Pa, Pb, which are output from the respective drive pulse shaping circuits in response to the driving method control signals Sa, Sb, Sc, Sd, and Se. From among Pc, Pd and Pe), the drive pulse required for each step motor is selected and output. This concludes the description of FIG. 3.

Reference numerals 213, 214, 215, and 216 are motor drivers, which alternately output motor drive pulses output from the motor drive pulse selection circuit to two output terminals of each motor drive circuit, and drive each step motor.

Reference numeral 217 denotes an input control and reset circuit, and performs processing of switch inputs of A, B, C, D, PA1, PA2, RB1, and RB2 and processing of input terminals of K, T, and R. When any one of A, B, C, and D or any one of RA1, RA2, RB1, and RB2 is input, a switch interrupt (Swint) is generated. Loss and reset of the interrupt factor at this time are performed by software. Each input terminal is _pulled down to V _ss and becomes data 0 in the open state and data 1 in the state connected to T _DD .

The K terminal is a specification switching terminal, and two types of specifications can be selected based on the data of the K terminal. The data of the K terminal is read by software.

The R terminal is a system reset terminal, and when the R terminal is connected to V _DD , the core CPU, frequency divider circuit and other peripheral circuits are forcibly set to the initial state by hardware.

The T terminal is a test mode change terminal, and 16 test modes for testing peripheral circuits can be switched by inputting a clock to the T terminal while the RA2 terminal is connected to V _DD .

The main test modes include power failure I confirmation mode, power failure II confirmation mode, reverse I confirmation mode, reverse II confirmation mode, correction drive confirmation mode, and chronograph 1/100 second confirmation mode. The motor drive pulse is automatically output to the pulse output terminal.

In addition to connecting the R terminal to V, the system reset can also be performed at the same time as input of the switch. In this IC, when either one of A or C and simultaneous input of B and RA2 are present, When one and RA2 and RB2 are simultaneously input, the system is configured to force a system reset by hardware.

In addition, as a reset function that can be processed by software, there are a divided circuit reset and a peripheral circuit reset. When the peripheral circuit reset is performed, the divided circuit is also reset.

Reference numeral 218 denotes an interrupt control circuit, which stores the memory until the read is performed according to the priority of each interrupt with respect to the switch interrupt, the chronograph interrupter, and the motor control interrupt, and the reset processing after the read.

Reference numeral 200 is a constant voltage circuit, and forms a constant voltage of about 1.2 V from the battery voltage (about 1.58 V) applied between V _DD and V _SS and outputs the VSI terminal.

This concludes the description of FIG.

As described in detail above, the CMOS-IC 20 has the following characteristics with respect to the driving of the stem motor, and is very excellent as a multifunction analog electronic clock IC of a multi-needle type.

1) It has motor drivers 213, 214, 215 and 216 and can drive four step motors simultaneously.

2) A driving control method control circuit 219, drive pulse forming circuits (221 to 225) and motor drive pulse selection circuits (234 to 237) are provided. Two kinds of reverse drive can be performed.

3) The driving reference signal forming circuit 220 is provided, and the driving speed of each step motor can be freely changed by software.

4) Motor clock forming circuits 226 to 229 corresponding to each of the four step motors are provided, and the number of moving pulses of each step motor can be set freely by software.

Next, a plan view of an embodiment of the multifunction analog electronic watch of the present invention is shown in FIG. In this embodiment, four step motors are realized in a multifunctional manner. 10 will be described below.

(1) is a fingerboard made of resin molding, and (2) is a battery. (3) is a step motor A for displaying a normal time, and is composed of a magnetic core 3a made of a high investment material, a coil wound around the magnetic core 3a, and a coil lead substrate and a coil frame in which both ends thereof are electrically conductive. A coil block 3b, a stator 3c made of a high investment material, and a rotor 4 made of a rotor magnet and a gear. (5, 6, 7, 8) are wheels 5, 4, 3, and 2, respectively, (9) fast wheels of dates, and (10) wheels. Wheel 2 and the wheel are located in the center of the watch body. By these lubrication structure, the minute display and the hour display of a normal time are performed in the center position of a watch body. 11 is a cross-sectional view showing the engagement state of the leap train for the normal time-hour display. As shown in the figure, the rotor gear 4a meshes with gear 5a, and gear 5b engages with gear 4a. The fourth gear 6b is engaged with the third gear 7a, and the third gear 7b is engaged with the second gear 8a. The gear ratio from the rotor gear 4b to the second gear 8a is 1/1800. The rotor 4 rotates half a second, so the second wheel rotates once every 3600 seconds or 60 minutes. It is possible to display the minutes at normal time. (11) is the minute hand fitted to the tip of the second wheel (8) for minute display. The second gear 8b is engaged with the shorthand gear 9a of the date, and the shorthand gear 9b of the date is engaged with the cylindrical wheel 10. The reduction ratio from the 2nd gear 8b to the toe wheel 10 is 1/12, and the time display of a normal time is attained. (12) is an hour hand fitted to the tip of the wheel 10 for visual indication. In Fig. 10, reference numeral 13 denotes a grass wheel arranged on the ninth-axis axis of the watch body, and the heat flux configuration is made by the rotor 4, the wheel 5, and the grass wheel 13; The second display of the normal time is performed on the axis of the clock body at 9 o'clock. 12 is a cross-sectional view showing the engagement state of the leap heat for this normal second display. As shown in the figure, the fifth gear 5b is engaged with the first gear 13a. The reduction ratio from the rotor gear 4a to the small gear 13 is 1/30. The rotor wheel 13 rotates 180 ° for one second, and the small wheel 13 is rotated once in 60 seconds for one second. It rotates by 6 degrees, and the second display of the normal time becomes possible. Numeral 14 denotes a small hand fitted to the tip of the small wheel 13 for seconds display.

In Fig. 10, reference numeral 15 denotes a step motor B for displaying a chronograph second hand, a coil wound on a magnetic core 15a made of a high investment material, a coil wound on the magnetic core 15a, and a coil lead substrate in which both ends thereof are electrically conductive. The coil block 15b which consists of a coil frame, the stator 15c which consists of a high investment material, and the rotor 16 which consists of a rotor magnet and a rotor gear are comprised. (17,18,19) are 1/5 second CG first middle wheel, 1/5 second CG second middle wheel, 1/5 second CG wheel, respectively, and 1/5 second CG wheel is the center of the watch body. It is located at the position. By these wheel heat constitutions, chronograph seconds are displayed at the center position of the watch body. 13 is a cross-sectional view showing the engagement state of the leap heat for the chronograph second display. As shown in the figure, the rotor gear 16a is engaged with the 1/5 second CG first intermediate gear 17a, and the 1/5 second CG first intermediate gear 17b is the 1/5 second CG second intermediate gear. Meshed with (18a). Further, the 1/5 second CG second intermediate gear 18b meshes with the 1/5 second CG gear 19a. The reduction ratio from the rotor gear 16a to the 1/5 second CG gear 19a is 1/150. In response to an electrical signal from the CMOS-IC 20, the rotor 16 rotates 180 degrees between 1/5 seconds. For this reason, the 1/5 second CG wheel 19 rotates 1.2 degrees 占 5 steps between 1/5 seconds and 1 second, and the chronograph second display every 1/5 seconds becomes possible. 21 is a 1/5 second CG needle fitted to the 1/5 second CG wheel tip for chronograph second display. The 1/5 second CG needle 21 also serves as a timer set needle for a timer time set. This timer operation is described later.

Reference numeral 27 denotes a step motor C for chronograph minute display and timer elapsed time second display. A coil block 27b made of a lead substrate and a coil frame, a stator 27c made of a high investment material, and a rotor 28 made of a rotor magnet and a rotor gear. Further, (29, 30) are the minute CG intermediate wheels and the minute CG wheels, respectively, and the minute CG wheels 30 are disposed on an axis in the 12 o'clock direction of the clock body. By these rotatory structures, the chronograph minute display and the second display of the timer elapsed time are performed on the 12 o'clock axis of the clock body. Fig. 14 is a cross-sectional view showing the engagement state of the leap heat for the chronograph minute display and the timer elapsed time second display. As shown in the figure, the rotor gear 28a is engaged with the minute CG intermediate gear 29a, and the minute CG intermediate gear 29b is engaged with the minute CG gear 30a.

The reduction ratio from the rotor gear 28a to the minute CG gear 30a is 1/30. In the chronograph mode, the rotor 28 rotates at a rate of 360 °, i.e., 180 ° x 2 steps, in one minute by an electric signal from the CMOS-IC 20. Therefore, the minute CG wheel rotates 360 ° (12 ° x 30 steps) in 12 ° or 30 minutes between 1 minute and 30 minutes of chronograph minute display is possible. Denoted at 31 is the minute CG needle fitted to the minute CG wheel tip for chronograph minute display. The combination of the minute CG needle 31 and the aforementioned 1/5 second CG needle 21 enables chronograph display of the minimum reading unit 1/5 and the maximum measurement 20 minutes. Next, in the case of the timer mode, the rotor 28 rotates in the reverse direction as in the chronograph mode by the electric signal in the CMOS-IC 20. This rotation is 180 degrees x 1 step between 1 second, and this minute CG needle 31 rotates by 1 second angle counterclockwise, and displays the timer elapsed time second of 60 weeks. At this time, the rotor 16 rotates by 180 ° x 5 steps in one minute in the opposite direction to the chronograph mode by the electric signal from the CMOS-IC 20. Thus, 1/5 second CG seconds ( 21) rotates in the counterclockwise direction at a rate of 6 'for 1 minute, and displays the elapsed time minutes for the timer. Although setting the timer time, each time the B switch 25 is pressed once in the state of the first stage of the second winding 23 in FIG. 10, the rotor 16 rotates 180 ° x 5 steps, for 1/5 second. The CG needle 21 rotates by 6 'units (eye minute unit) and displays a timer setting time of up to 60 minutes.

FIG. 10 is a step motor D for displaying the alarm setting time, and a coil lead board and a coil wound on the magnetic core 32a and the magnetic core 32a made of a high investment material, and both ends thereof so as to conduct conductively. It consists of a coil block 32b made of a frame, a stator 32c made of a high investment material, and a rotor 33 made of a rotor magnet and a rotor gear. Also, (34, 35, 36, 37) are AL intermediate wheels, AL minute wheels, AL date wheels, and AL wheels, and AL minute wheels 35 and AL wheels 37 are 6 on the watch body. It is arrange | positioned on the axis of time direction. According to these wheel sequence configurations, the set time display is performed on the axis of the clock body at the 6 o'clock direction. Fig. 15 is a sectional view showing the engagement state of the leap heat for this alarm setting time display. As shown in the figure, the rotor gear 33a is engaged with the AL intermediate gear 34a, and the AL intermediate gear 34b is engaged with the AL minute gear 35a. The AL gear 35b is engaged with the short gear 36a of the AL date, and the gear 36b of the AL date is meshed with the AL wheel 37. The reduction ratio from the rotor gear 33a to the AL gear 35a is 1/30, and the reduction ratio from the AL gear 35B to the AL wheel 37 is 1/12. Reference numeral 38 denotes an AL minute hand fitted to the tip of the AL wheel 35, and reference numeral 39 denotes an AL hour hand fitted to the tip of the AL barrel 37.

When the second winding is in the first stage, the alarm B mode is entered, and when the C switch 26 is pressed, the rotor 23 rotates by 180 degrees in response to an electrical signal from the CMOS-IC 20. The AL buddha rotates by 0.5 °. In this way, the alarm set time can be set up to 12 hours in 1 minute increments. If the set alarm set time matches the current time, the alarm sounds. In Alarm B mode, 12 hours have elapsed after the alarm sounds, and if the reset alarm set time matches the current time, the alarm sounds. When the second winding is in the 0th stage, the alarm A mode is set, and when the alarm is not set, the AL minute hand 38 and the AL hour hand 39 display the current time. In this case, the rotor 33 rotates 180 degrees every minute by the electric signal from the CMOS-IC 20. Therefore, the AL minute hand 38 performs one minute of sleep. When the C switch is pressed, the alarm is set as in the alarm A mode, and the minute minute hand of the AL minute hand 38 is stopped. If the set alarm time coincides with the current time, an alarm sound different from that in the alarm B mode is sounded, the alarm set state is canceled after the sound, and the AL minute hand 38 moves for another minute. If the alarm set time matches the current time during correction, the alarm set state is canceled. In addition, if the notification set time and current time coincide with the early revision, the correction is stopped.

This concludes the description of FIG.

FIG. 16 shows a circuit connection diagram of the CMOS-IC 20 and other electric elements. In Fig. 16, reference numeral 2 denotes a silver oxide battery (SR 927W), 3b denotes a coil block of step motor A, 15b denotes a coil block of step motor B, 24 denotes an A switch, and 25 denotes a B switch. (26) is C switch, 27b is coil block of step motor C, 32b is coil block of step motor D, 55 and 56 are buzzer driving elements, 55 is booster coil, ( 56 is a mini-mold transistor with a protection diode, 57 is a 0.1 μF chip capacitor for suppressing voltage fluctuations of a constant voltage circuit built in the CMOS-IC 20, and 58 is a CMOS-IC 20. Ultra-small tuning fork crystal oscillator serving as a power source of the built-in oscillation circuit, 46a is a switch formed in a part of the latch 46, 59a is a switch formed in a part of the second mandarin duck (59; 64 is a piezoelectric buzzer attached to the inner pig (pig-shaped part) of the watch case although not shown in FIG. The switches 24, 25, and 26 are push button type switches and can be input only at the push. In addition, the switch 46a is a switch which is interlocked with the first winding 22, and is configured to close with the RA1 terminal in the first stage of the first winding 22, close with the RA2 terminal in the second stage, and open in the normal position. . In addition, the switch 59a is a switch which is interlocked with the second winding 23. The switch 59a is configured to close the RB1 terminal at the first stage of the second winding 23, to close the RB2 terminal at the second stage, and to open in the normal position. have.

Fig. 17 is an external view of the complete body of the multifunctional electronic watch of this embodiment. The means and operation method of the present embodiment will be briefly described based on the flowcharts of FIGS. 17 and 18 to 22.

In FIG. 17, reference numeral 40 denotes an outer case and 41 denotes a dial. Further, on the dial, 42 is a normal second time display part, 43 is a chronograph minute display and a timer elapsed time second display part, and 44 is each display part at the time of alarm setting.

First, although it is a normal time, it is indicated by the small seconds hand 14, the minute hand 11, and the hour hand 12 which perform every second hand movement as mentioned above. Vision alignment is made possible by drawing out the 1st roll 22 to 2nd stage. At this time, the number 4 wheel 6 is defined by the defining lever 47 engaging with the mandarin duck 45 and the latch 46 shown in FIG. 10, the rotor 4 stops, and the minute hand of the small hand stops. do. In this state, when the first winding 22 is rotated, the rotational force is transmitted to the inner wheel 9 of the date through the drum wheel 48 and the cycad wheel 50. Here, the second gear 8a has a constant torque and is coupled with the second gear 8b, so that even if the fourth wheel 6 is defined, the cycad wheel 50, the inner wheel 9 of the date, and the second The gear 8b and the wheel 10 rotate.

Therefore, the minute hand 11 and the hour hand 12 rotate, and can be set to arbitrary times.

18 is a flowchart for displaying a normal time. As shown in Fig. 18, when the 1 Hz interrupt is input, it reads whether the switch RA2 is off or not, and when the RA2 is off, the electrostatic correction drive of the step motor A is set in the motor driving method control circuit 219. Then, the number of revolutions 1 is set in the motor clock control circuit A226. When the switch RS2 is on (time corrected state), the motor drive is stopped, and the frequency divider circuits 208 and 209 are instantaneously reset so that the motor is driven 1 second after the time when RS2 is off.

Fig. 19 shows a flowchart of the chronograph function. In addition, "CG" used in FIG. 2 is an abbreviation of chronograph. In addition, "CG start" shows the split display canceling state during chronograph measurement. When the second winding 23 is in the normal position (when RB1 and RB2 are off together), the chronograph mode is entered, and the start and stop of chronograph measurement are repeated each time the A switch is input. When the chronograph measurement starts, the CG 1/5 second counter formed in the part of the data memory 204 by the CG interrupt is +1, and the 1/5 second CG hand 21 is driven at the 1/5 second angle. At the same time, if the 1/5 second counter counts for one minute, the CG minute counter +1, which is also formed in a part of the data memory 204, +1 and the minute CG 31 is driven at one minute angle. In addition, when the B switch is input at the "CG start", it is in the split display state, and when the B switch is input in the split display state, it is in the "CG start" state, and it is 1/5 second CG needle 21 and minute CG needle 31. Is dispatched until the measurement time is displayed. When the B switch is input while the chronograph measurement is stopped, the chronograph measurement is reset and each CG hand is fed until the 0 position is displayed. In addition, the flowchart of the early shipping method is shown in the flowchart of FIG.

20 shows a flowchart of the timer function. The timer setting time is indicated by the 1/5 second CG hand 21. When the second winding 23 is in the first stage (when RB1 is on), the timer mode is entered.When the B switch is input while the timer is in the set state, the timer set time is increased by one minute, and the 1/5 second CG needle 21 is used. This one minute unit (5 steps) is immersed. The scale on the dial 41 indicated by this 1 / 5-second CG needle 21 indicates the timer setting time, and setting up to 60 minutes is possible. The start and stop of the timer are performed by the A switch 24. When the timer operation starts, the minute CG hand 31 moves every minute for one second in the counterclockwise direction, and the 1/5 second CG hand 21 moves for one minute in the counterclockwise direction to display the elapsed timer time. In the last minute, when the timer is set for 1 minute, the minute CG needle 31 stops, and the 1/5 second CG needle 21 subtracts every 1 second, and a notice sound sounds from 3 seconds before the final time. When the timer reaches the end of the timer operation.

21 shows a flowchart of the alarm function. As shown in FIG. 21A, when the C switch 26 is pressed while the second winding 23 is in the 0th or 1st stage, that is, RB2 is off, the motor drive pulse control circuit D 233 is commanded by a command from the CPU. The electrostatic drive II is selected, and 15 is set in the register (hereinafter, the motor pulse register) of the trigger forming circuit D 233 to start correcting the feeding of the minute hand at the alarm. When the alarm A mode, i.e., the second winding is in the 0th stage and is in the alarm non-set state (alarm ring prohibition state), the time at which this correction is started is the alarm set time, and the alarm ring prohibition state is released, i.e., the alarm set state. When the motor pulse is output 15 times, a control interrupt is generated by the trigger forming circuit S233. When the control interrupt occurs, as shown in Fig. 21B, in the alarm B mode, 15 is added to the alarm time B, 15 is reloaded in the motor pulse register, and the correction is continued. In the alarm A mode, if the difference between the present time and the alarm time A is 15 or more, 15 is added to the alarm time A. As a result, if the difference between the present time and the alarm time A becomes less than 15, the difference is set in the motor pulse register. In that case, the minute hand indicates the current time at the time of the next control interrupt. Therefore, set 0 in the motor pulse register to stop the modification, prohibit the alarm sounding, and cancel the alarm set state. When the C switch is removed, the up counter 2262 (hereinafter, the motor pulse up counter) is read as shown in FIG. 21A, and the feeding of the AL minute hand 38 stops. At this time, since the AL minute hand 38 advances by the read value from the time when the last control interrupt occurred, the correction is performed. In the alarm A mode, when the alarm time coincides with the current time at this point, the alarm is prohibited and the alarm is not set. The alarm is sounded when the alarm time and the current time are known by counting the 1 Hz interrupt as shown in Fig. 21C. However, if the alarm ringing is prohibited in the alarm A-dod, the alarm ringing is not performed and the alarm AL minute hand 38 is made to move for 1 minute. In the alarm A domain, after the alarm sounds, the alarm set is prohibited to cancel the alarm set state.

In the present embodiment, the alarm control means has the current time, the alarm set time A, and the alarm set time B as absolute values, respectively. For example, the difference between the alarm set A and the current time, the alarm set time B, and the current time is different. As mentioned above, it is possible to have and control the relative value.

In addition, in the present embodiment, the control means uses a CPU, but instead, the control means can be realized only by a logic circuit.

The normal time correction is also performed via AL (49, 51) shown in FIG. 10 by rotating the second winding in the second stage state.

22 shows a flowchart of a method of driving each motor. FIG. 22A is a motor driving method when the number of impregnations is 14 or less, and FIGS. 22B and 22C are driving methods of fasting (128 Hz) of 15 or more. In addition, the "motor pulse register" used in the figure is that of the register 2221 in FIG.

This concludes the description of the embodiment.

Next, a second embodiment of the present invention will be described.

In this embodiment, the liquid crystal driver and latch 3001 and the liquid crystal display device 3002 shown in FIG. 23 are added to the first embodiment, and the current time, second time different from the current time, calendar, The alarm time, timer time, mode, chronograph time, and the like are digitally displayed by the liquid crystal display device 3002.

As described above, according to the present invention, one or more sets of display instructions are displayed by the alarm control means and the step motor in the alarm non-set state, and the display instructions for displaying the current time are in the alarm set and in the alarm set. After the alarm is set, the alarm set time is displayed, and after the alarm is set, the alarm is not set, and the display indicator displays the current time again. The operation for canceling the alarm and the prohibition of ringing when an alarm is set can be omitted, and the operation can be simplified.

In addition, since the operation is simple, wear of the switches is less, and the long-term reliability of the watch can be improved.

In addition, since the alarm time is displayed in the alarm set state and the current time is displayed in the alarm non-set state, it is possible to know whether or not the alarm set state is provided without having a special mode display means. Therefore, the user can know whether or not the next operation needs to be performed without looking at the display.

In addition, the mode can be known only by listening to the alarm sound by changing the alarm sound by the mode. Therefore, even if the user does not look at the display, it is possible to know whether it is necessary to perform the operation next time. In addition, the ringing sound of the alarm can be changed in accordance with the purpose of the alarm.

Also, if the alarm set time and current time coincide with the set of alarm set time, the alarm set state is canceled and the modification of the alarm set time is stopped, so that the alarm set is not performed without any special operation and the display state is checked. Allow the state to be released.

As described above, according to the present invention, the marketability of the electronic clock with alarm can be improved.

Claims (7)

The current time is displayed in the alarm non-set state in the step motors (3, 4, 32, 33) of the complement that displays the normal time and the display instructions (38, 39) of one or more sets, and the current time is displayed. The display instructions 38 and 39 display the alarm set time during or after the alarm set, and at the same time as the alarm non-set state after the alarm, the display instructions 38 and 39 display the current time again. At least one display guide 11, 12, 38, 39 driven by each step motor, and the first and second external operating means 22, 23 are manually operated stems and a third external. The operation means 26 includes a plurality of external means 22, 23, 26 which are spring-biased buttons, and an alarm control means 20. The alarm control means 20 is software The program memory 202 for storing the data, the data memory 204 for storing the position of each instruction, and the motor drive pulse. A plurality of motor drivers 213, 214, 215 and 216 for driving the stepper motor, a motor drive control circuit 212 for generating motor drive pulses for each motor driver according to a software command, and a buzzer drive signal. An interrupt control circuit which performs the memory generation until the reading is performed in accordance with the priority of each interrupt with respect to the generated name generator 210 and the switch interrupt, the chronograph interrupt, and the motor control interrupt ( 218) comprising an electronic clock with an alarm. The electronic clock with an alarm according to claim 1, further comprising means for setting an alarm non-set state when the alarm set time and the current time coincide with each other by the set of the alarm set time by the alarm control means. The electronic clock with an alarm according to claim 1, further comprising means for stopping the feeding set of the alarm set time when the alarm set time and the current time coincide among the feeding sets of the alarm set time by the alarm control means. The alarm ring function shown in claim 1 and the alarm set time are maintained even after the alarm is sounded by the alarm control means. Then, when the alarm set time and the current time coincide, the alarm sounds again. Electronic clock with an alarm, characterized in that it has a selection means. The method of claim 4, wherein the alarm set time is maintained even after the alarm is sounded, and when the alarm set time and the current time coincide with each other, the alarm sound is generated by the function of sounding the alarm again, and the alarm is not set after the alarm sound. Electronic clock with alarm, characterized in that the alarm ringing sound by the function is different. The electronic clock with alarm according to claim 1, further comprising a digital indicator (3002). A step motor, a display guide driven by the step motor, an external operation member, and an alarm control means, wherein the alarm control means includes motor driving means for driving the step motor based on an input signal of a predetermined period; A current time counter in which the current time is stored, an alarm time counter in which an alarm setting time is stored by an operation of the external operation assistant, a match between the current time counter and the alarm time counter, and outputs a coincidence detection signal; Matching means for detecting, an alarm sound means for ringing an alarm type to which the matching detection signal is input, and holding means for holding and outputting the match detection signal until the contents of the alarm time counter are changed by the external operation member; And a second input signal having a predetermined period based on the output signal of the holding means as the first input signal. A second gate means for outputting a signal input by at least one of a signal input by an operation of the second gate means and an external operation member and an output signal of the first gate means to the motor driving means; Electronic clock with alarm, characterized in that configured.

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