KR950002303B1 - Decoder with duel coding mode - Google Patents

Abstract

The coder for coding the binary data to the BnZS (Bipolar with n Zero Substitution) and HDBn (High Density Bipolar Codes) according to the mode selection includes a coding mode shifter (102) outputting the serial stream data in parallel and the mode shift data (Qd) after shifting the binary data with a first or second mode, a decoder (104) outputting a first and a second coding control signals (Y1-2) after counting the bipolar bit of the mode shift data, a violation detector (106) outputting the violation detecting signal (X) corresponding to the coding mode after decoding the first and second mode shift data, and a generator (108) generating the binary data with the coding mode after combining the X, Qd, and the coding control signals.

Description

Encoder with Dual Coding Mode

1 is a circuit diagram of an encoder having a dual coding mode according to the present invention.

2 is an operational waveform diagram of FIG. 1 according to a first mode.

3 is an operational waveform diagram of FIG. 1 according to a second mode.

TECHNICAL FIELD The present invention relates to a data transmission coder (CODER), and in particular, binary data can be coded with a code of Bipolar with "n" Zero Substitution (BnZS) and a code of Hish Density Bipolar Codes (HDBn) by mode selection. And an encoder having a dual coding mode.

In general, BnZS coding and HDBn coding are coding schemes used for transmitting PCM modulated binary data information. B3ZS coding is widely used in North America, which uses a 24-channel switching scheme, and HDB3 coding uses a 32-channel switching scheme. Widely used in Europe.

The B3ZS coding and HDB3 coding described above have a bit of a vibration bit "V" when the information of "O" is greater than or equal to a certain number in order to prevent data transmission error when the "O" binary information is more than a certain number of bits. Insertion transfer is allowed.

B3ZS coding converts "OV" or "BOV" when the number of consecutive 'O's is' 3 ', and HDB3 coding converts it to "OOV" when the number of consecutive' O's is '4'. Or "BOOV".

In other words, B3ZS and HDB3 coding

As shown above, if the number of bipolar bits "B" between "V" and "V" is held, "OOO or OOOO" is converted to OOV (BVS) or OOOV (HDB), and even if "BOV" or "BOOV" Is converted to.

Thus, * 1 and * 2 in the table may be "O" or "B" depending on the number of Bs between V and V of the preceding data.

The B3ZS coding circuit and the HDB3 coding circuit which perform the above coding are manufactured and produced by the respective coding circuits, and are in the form of one chip.

As described above, the B3ZS coding circuit and the HDB3 coding circuit are separately manufactured so that the two coding schemes can be used in a communication system that uses a 24 channel communication method having a 1.54 Mbps transmission rate and a 32 channel communication method having a 2.048 Mbps transmission rate. If you want to use has been a problem that takes many parts.

Accordingly, an object of the present invention is to provide a coder having a dual mode capable of coding binary information into a BnZS code and an HDBn code by selecting a coding mode.

Another object of the present invention is to provide a circuit that counts the number of consecutive " O " bits in accordance with the selection of a coding mode and generates a bit of violinization according to the mode.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is an arc diagram of an encoder having a dual coding code according to the present invention, which converts binary information input by a coding mode selection signal into first and second modes, converts serial stream data into parallel data, and outputs the parallel data. At the same time mode and the shift data coding mode shifter 102 to output a (Q _D), the mode cyst data by counting the bipolar bits of the (Q _D), the first and second outputs a coding control signal (Y1) (Y2) Violation for decoding the bipolar coefficient state decoder 104 and the first and second mode shift parallel data output from the coding mode shifter 102 and outputting a vibration detection signal X corresponding to the coding mode. A code for logically combining the detector 106, the detected vibration signal X, the mode shift data Q _D , and the first and second coding control signals to code the binary information in the coding mode. It consists of a data generator 108.

The coding mode shifter 102 of FIG. 1 configures a latch circuit 10 for firstly delaying input binary information DiN, and logics the first delayed information and the vibration detection signal X. Selects the second delayed information in response to a logical sum gate 12 for combining output, a latch circuit 14 for outputting a second delay of the output of the logical sum gate 12, and a second coding mode signal, A selectable latch circuit 16 for outputting a third delayed signal, a fourth delayed output after selecting the second delayed information in response to a first coding mode signal, and outputting a fourth delayed signal in response to a second coding mode signal; And a select enable latch circuit 18 for outputting mode shift data with a fourth delay of information.

The bipolar count state decoder 104 selects and delays the first predetermined state signal by the mode shift data Q _D output from the select enable latch circuit 18 in the coding mode shifter 102. The AND gate 22 and the AND gate 22 outputting the first coded signal Y1 by ANDing the latch 20, the output of the select enable latch 20, and the vibration detection signal X, respectively. And a NOR gate 24 for outputting a second coded signal Y2 by performing negative logic on an output and the fourth delay information Q _D.

The violation detector 106 comprises a noar gate 26 which negatively combines the first, second, third, and fourth delay information which are respectively delayed and output from the coding mode shifter 102, and detects the violation state. And a latch circuit 28 for delaying and outputting the output of the NOA gate 26.

The code data generator 108 is composed of an oragate 30, 34, 36, a selectable latch circuit 32, and two latch circuits 38, 40. As shown in FIG.

FIG. 2 shows the waveforms of each part of FIG. 1 when operating in the B3ZS coding mode.

FIG. 3 illustrates the waveforms of the parts of FIG. 1 when operating in the HDB3 coding mode as an example of the first coding mode.

Hereinafter, the operation of FIG. 1 according to the present invention will be described with reference to FIGS. 2 and 3.

[Example of operation of B3ZS coding]

As shown in FIG. 2, when the code mode signal select (CS) is set to " 1 " (B3ZS coding mode), each of the select enable latch circuits 16 and 18 is connected to the terminal D _A. The input signal is selected, and the selected signal is delayed and output by the clock CLK input to the clock terminal.

Therefore, when the binary data DiN having a continuous " O " is continuously input 3 bits as shown in the second diagram while the B3ZS coding mode is selected, the latch circuits 10, 14, 16 and 18 connected in series are connected. Their outputs are all "O" as in the second diagram. At this time, the NOA gate 26 outputs the vibration bit as shown in FIG. 2 at the position where the signal of " O " is continuously input for three bits. The detected vibration bit is input to the latch circuit 28 through the oragate 12.

By the above operation, the select enable latch circuit 20 outputs the first state signal as shown in FIG. 2 by the signal output from the select enable 18, and the AND gate 22 detects the detected bio. And outputs the first coding control signal Y obtained by logically multiplying the conversion bit " V " (X) with the first state signal.

That is, the bipolar count state decoder 104 counts the number of bipolar bits "B" (bipolar) between the vibration bits "V" and the vibration bits "V", and inputs binary information if the number of bipolar bits "B" is odd. The first and second coding control signals Y1 and Y2 are generated together with the second degree to convert OOV to 'OOV' and to convert to 'BOV'.

When the first coding control signal Y1 is "1", it indicates that the number of bipolar bits between the vibration bit "V" and the vibration bit "V" is even. Output a control signal to convert to '.

Accordingly, the B3ZS coded data (cod DT) of the input binary information is output in balance with Dout ⁺ and Dout ^- as shown in FIG.

[B3ZS Coding]

As shown in FIG. 2, when the coding mode signal (code select) CS is set to " O " (HDB3 coding mode), each of the select enable latch circuits 16 and 18 is input to the terminal D _B. The signal is selected, and the selected signal is delayed and outputted by the third clock by the clock CLK input to the clock terminal.

Therefore, when FIG. 1 is operated in the HDB3 coding mode, the four latch circuits 10, 14, 16 and 18 connected in series are operated by a 4-bit shift register as shown in FIG.

Therefore, when the input binary information DiN is continuously 'O' as in the third degree, the output X of the NOA gate 26 becomes '1' and applies it to the latch circuit 14 input.

At this time, the bipolar coefficient state decoder 104 counts the number of " B " between the " V " The first and second coding control signals Y1 and Y2 are generated to be defended.

That is, if the output Y1 is '1', it indicates that the number of Bs between 'V' is even and converts to 'BOOV' and if it is 'O', it outputs a control signal to convert to 'OOOV'.

Accordingly, the HDB3 code data code DT corresponding to the binary information input as shown in FIG. 3 is output as Dout ⁺ and Dout ^- as shown in the waveform diagram of FIG.

As described above, the present invention can be used as a B3ZS, HDB3 coder with a simple hardware configuration can be usefully used in a circuit that can be used in both North American and European methods.

Claims (4)

In the encoder having the dual coding mode, the binary information input by the coding mode selection signal is shifted to the first and second modes to output serial stream data in parallel and to output the mode shift data Q _D. A coding mode shifter 102, a bipolar coefficient state decoder 104 that counts bipolar bits of the mode shift data Q _D and outputs first and second coding control signals Y1 and Y2, and the coding A vibration detector 106 for decoding the first and second mode shift parallel data output from the mode shifter 102 and outputting a vibration detection signal X corresponding to a coding mode, and the detected vibration signal times, characterized by consisting of a (X) and the mode shift data (Q _D), the code data generator 108 for the first and second coding the binary information by the logical combination of the coding control signal to the encoding mode output . The method of claim 1, wherein the code mode shift 102 is a latch circuit 10 for outputting a first delayed input binary information DiN, and the first delayed information and the vibration detection signal X. A logic sum gate 12 for combining output, a latch circuit 14 for outputting a second delay of the logic sum gate 12, and a third delay by selecting the second delayed information in response to the second coding mode signal. An output of the select enable latch circuit 16 and outputting the second delayed information as fourth delay information in response to the first coding mode signal, and selecting the third delayed information in response to the second coding mode signal. And a select enable latch circuit (18) for delaying the fourth delay information and outputting the mode shift data. 3. The select enable latch circuit (20) according to claim 2, wherein the bipolar count state decoder (104) selects and delays the first predetermined state signal by the mode shift data output from the select enable latch circuit (18). And an AND gate 22 and an output of the AND gate 22 that output the first coded signal Y1 by ANDing the output of the select enable latch circuit 20 and the vibration detection signal X. And a NOR gate (4) for outputting a second coded signal (Y2) by performing negative logic combining the fourth delay information (Q _D ). The vibration state of claim 2 or 3, wherein the violation detector 106 negatively combines the first, second, third, and fourth delay information, which are delayed from the mode shifter 102, respectively. And a latch circuit (28) for delaying and outputting the output of the noble gate (26).