KR950002190B1 - Semiconductor device isolation method - Google Patents

Abstract

The method includes the steps of sequentially forming an oxidation stopper film (2), a 1st insulating film (5) and a 2nd insulating films (10) on a substrate (100), selectively etching the films (5,10) to form a narrow opening part (20) of 0.5 micron and a wide opening part (25) of 0.9 micron, forming spacers (17) on the inner side walls of openings (20,25), etching the substrate (100) to form a narrow trench (30) and a wide trench (35), thermally oxidizing the inner sides of trenches to form a 1st thermal oxide film (4) to bury the inner sides of trenches, partially filling the trenches with 1st material layer (45), and forming a 2nd thermal oxide film (50) on the layer (45), thereby preventing the bird's beaks and reducing the size of opening part to reduce the device size.

Description

Device Separation Method of Semiconductor Device

1 is a simplified layout diagram showing device formation regions and device isolation regions of a semiconductor device.

2A to 2E are process flow charts showing a process for forming a device isolation region of a semiconductor device according to the prior art.

3A to 3G are process flowcharts showing a process of forming an element isolation region of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device capable of minimizing device isolation regions of a semiconductor device.

Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large-capacity memory devices has been progressed. It has been promoted by a memory cell study. In particular, the reduction of the device isolation region that separates devices has emerged as one of the important items in the technology of miniaturization of memory devices.

Conventional device isolation techniques have recently been dominated by LOCOS (LOCal Oxidation of Silicon) technology, which selectively grows thick oxide films on semiconductor substrates to form device isolation regions. However, the LOCOS technique cannot reduce the width of the device isolation region due to side diffusion of the device isolation region and bird's beak. Thus, in a large-capacity memory device whose device design dimension is reduced to less than submicron, Since the LOCOS technology is not applicable, a new device isolation technology is needed.

Accordingly, with the necessity of a new device isolation technology and the development of etching technology, device isolation using a trench capable of electrically separating devices by forming grooves having a width of 1 μm or less and a depth of several μm in a semiconductor substrate is formed. Technology came out. The device isolation technology using this trench allows the device isolation area to be reduced by nearly 80% compared to the conventional LOCOS technology.

1 is a simplified layout diagram for forming an element formation region and an isolation region of a semiconductor device.

Referring to FIG. 1, the mask pattern P for dividing the device isolation region from the active region is shown. The inside of the box indicated by 'P' corresponds to the active region in which the element is formed. The portion of corresponds to a device isolation region in which a field oxide film or a trench for device isolation is formed.

In general, in a large-capacity semiconductor device, due to high integration, the distance between the mask patterns P defining the device formation region is not constant when the AA 'line is referenced, and it is different from each other such as' B' and 'C'. Can be. That is, it can be seen that field oxide films or trenches having different sizes should be formed.

2A to 2E are process flow charts showing a process of forming an element isolation region of a semiconductor device according to the prior art, which is a cross-sectional structure taken along the line AA 'of FIG.

First, referring to FIG. 2A, the pad oxide film 1, the first insulating film 5, and the second insulating film 10 are sequentially layered on the semiconductor substrate 100. In this case, for example, the first insulating layer uses silicon nitride, and the second insulating layer 10 uses high temperature oxide (HTO) as an insulating material. Subsequently, a photoresist is applied, masked, and developed on the second insulating film 10 to form a first mask pattern 15 as shown by reference numeral P of FIG. 1, and the first mask pattern 15 is applied to the first mask pattern 15. The second insulating film 10 and the first insulating film 5 are selectively etched.

Referring to FIG. 2B, the pad oxide layer 1 is subjected to ion reactive etching (RIE) by removing the first mask pattern and using the etched second insulating layer 10 and the first insulating layer 5 as a second mask pattern. Reactive Ion Etching to expose a predetermined region of the semiconductor substrate 100 so that the width of the semiconductor substrate 100 is the same as the opening of the reference numeral B of FIG. 1 (hereinafter referred to as a narrow opening), and the opening of the same reference numeral C of the following (hereinafter, Wide openings). Subsequently, the semiconductor substrate 100 is etched through the narrow and wide openings, thereby forming a trench 20 having a width B (hereinafter referred to as a narrow trench) and a trench 25 having a width C (hereinafter, referred to as a wide width). A trench). At this time, the second insulating film 10 is etched according to the etching selectivity during the etching process of the pad oxide film 1 so that a small amount remains.

Referring to FIG. 2C, the inner walls of the narrow trenches 20 and the wide trenches 25 are thermally oxidized to form the first thermally oxidized film 30 of 500 를 or less. For example, polycrystalline silicon is applied to a predetermined thickness to form the first material layer 35 and then anisotropically etched so that it remains only inside the trench. At this time, it can be seen that the center portion of the wide trench is recessed like A.

Referring to FIG. 2D, the field oxide layer 40 is formed by thermally oxidizing the first material layer in the upper regions of the trenches 20 and 25. At this time, the upper region of the narrow trench 20 is planarized, but the field oxide film 40 on the wide trench 25 is recessed like A 'according to the former form recessed.

Referring to FIG. 2e, the second insulating film and the first insulating film are treated with a VOE (Buffered Oxide Etchant) solution or a phosphoric acid (H ₃ PO ₄ ) solution to remove the sacrificial oxide film, and the stress is compensated again. A portion of the sacrificial oxide film and the field oxide film 40 are etched to complete the device isolation region. Again, the center portion of the upper portion of the wide trench is recessed like A ″.

In the device isolation region of the semiconductor device manufactured by the conventional technique as described above, the surface of the device isolation region such as A ″ in FIG. 2e is not flat and the conductive material is not formed when the gate electrode or the bit line is formed. It is difficult to deposit, or the conductive material moves along the uneven surface and the thickness of the conductive layer at the edge and the middle portion is different, so that the resistance value of the conductive layer is increased or the conductive material is applied to the uneven surface. When removing unnecessary parts by etching, the conductive material is not completely removed along the sidewall of the step by the shading effect of the lower stepped step. (stringer) is generated, and as a result, the electrical characteristics and reliability of the semiconductor device are degraded. In addition, as shown by reference numeral R of FIG. 2e, the burying phenomenon cannot occur and the size of the device isolation region cannot be reduced. In this process, the Buzzbeek becomes larger.

Accordingly, an object of the present invention is to provide a device isolation method that can solve the problems of the prior art as described above to be electrically stable and minimize the device isolation region.

A device isolation method of the present invention for achieving the above object is a step of sequentially stacking an oxide blocking film, a first insulating film, a second insulating film on a semiconductor substrate, by selectively etching the first insulating film and the second insulating film narrow openings And forming a wide opening, forming a spacer on an inner wall of the opening, etching a semiconductor substrate using the spacer as a mask, and forming a narrow trench and a wide trench, and thermally oxidizing the inside of the trench. Forming a secondary thermal oxide film to bury the inside of the narrow trench, and at the same time to partially fill the interior of the wide trench, a first material capable of oxidizing the interior of the wide trench filled with the primary thermal oxide film A step of filling the layer and a step of oxidizing an upper portion of the first material layer to form a second thermal oxide film; Characterized in that made.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3A to 3G are process flow charts showing a process of forming an element isolation region of a semiconductor device according to the present invention.

First, referring to FIG. 3A, as a material for forming an oxide blocking film on the semiconductor substrate 100, for example, oxide nitride film (Oxynitride-silicon: SiOxNY) is deposited to a thickness of about 240 GPa. ), And as a material for forming the first insulating film thereon, for example, silicon nitride is deposited to a thickness of about 1500 kPa to form the first insulating film 5. Subsequently, as a material for forming the second insulating film on the first insulating film 5, for example, the HTO film 10 is formed to a thickness of about 1000 GPa, and then a photoresist is applied thereon, such as mask exposure and development. The first photoresist pattern 15, which is the same as the mask pattern P of FIG. 1, is formed thereon, and the second insulating film 10 is selectively etched by applying it as a mask to narrow the opening of 0.5 mu m in the case of a 64 Mb semiconductor device. 20 and a 0.9 m wide opening 25 are formed in the case of a 256 Mb class semiconductor device, and a narrow opening 20 of 0.4 m and a wide opening 25 of 0.6 m are formed.

Referring to FIG. 3B, the first photoresist pattern is removed, the first insulating layer 5 is etched using the second insulating layer 10 as a mask, and then a third insulating layer is formed on the entire surface of the resultant. Silicon nitride, which is the same material as the first insulating film, is deposited to a thickness of about 2000 microseconds to form a third insulating film 16.

Referring to FIG. 3C, spacers 17 are formed on inner walls of the openings 20 and 25 by anisotropically etching the entire surface of the structure on which the third insulating layer is formed. At this time, the spacing between the spacers formed on the inner wall of the narrow opening 20 is 0.3 [mu] m for the 64 Mb class semiconductor device and 0.1 [mu] m for the 256 Mb class semiconductor device and between the spacers formed on the inner wall of the wide opening 25. The spacing is 0.6 mu m for the 64 Mb class semiconductor elements and 0.4 mu m for the 256 Mb class semiconductor devices. The third insulating layer 10 is etched according to the etching selectivity, so that a small amount remains. Subsequently, the oxide blocking film 2 is etched using the spacer 17 as a mask.

Referring to FIG. 3D, the semiconductor substrate 100 is etched using the spacers 17 as a mask to form narrow trenches 30 and wide trenches 35. Subsequently, the remaining portion of the second insulating film is removed by treatment with a BOE solution or a phosphoric acid solution. By reducing the size of the opening formed by the photo process, the spacer may be more highly integrated and overcome the limitation of the size that cannot be formed by the photo process.

Referring to FIG. 3E, the inside of the trenches 30 and 35 is thermally oxidized to form a first thermal oxide film 40 of about 1000 kV, so that the inside of the narrow trench 30 is formed in the first thermal oxide film. The inside of the wide trench 35 is partially embedded in the inner wall of the thick primary thermal oxide film 40. Subsequently, as a material capable of being oxidized on the entire surface of the resultant after the first thermal oxide film 40 forming process, for example, polycrystalline silicon is applied to a thickness of 7000 kPa to form the first material layer 45 and the first material again. The layer 45 is anisotropically etched so that it remains only inside the trenches 30 and 35. In this case, the first material layer 45 may remain in a portion of the upper portion of the narrow trench 30 when the narrow trench 30 is not completely filled with the first thermal oxide film 40.

Referring to FIG. 3f, a second thermal oxide film 50 having a thickness of about 1000 ns to about 1500 ns is formed by thermally oxidizing polycrystalline silicon on the trenches 30 and 35. Subsequently, the antioxidant film, the first insulating film, and the spacer are wet-etched and removed.

Referring to FIG. 3g, in order to compensate for stress that may occur during the wet etching process, a sacrificial oxide film is grown, and a portion of the sacrificial oxide film and the second thermal oxide film 50 are wet-etched again with BOE solution to separate the device isolation region. To complete. The size of the isolation region is 0.35 µm and 0.8 µm in the narrow trench and the wide trench in the case of the 64 Mb semiconductor device, and 0.25 µm in the narrow trench and the wide trench in the 256 Mb semiconductor device, respectively. , About 0.5 μm.

Therefore, in the device isolation method according to the present invention as described above, a thick thermal oxide film is formed in the inside of the trench so that the insulator in the center portion of the wide trench, which is a problem in the prior art, is not embedded in the thick thermal oxide film. The planarization characteristics of the device isolation region may be improved by filling only a portion of the region with polycrystalline silicon. In addition, by using oxynitride silicon, which is a non-oxidized material, in place of a pad oxide film that is oxidized as in the field oxide film formation to generate a buzz beak, it is possible to prevent the occurrence of burj beak.

In addition, by forming a spacer on the inner wall of the opening with a nitride film to reduce the size of the opening, it is possible to overcome the limitation of the size which is highly integrated and cannot be formed by the photo process.

The present invention is not limited to the above embodiments and various modifications can be made by those skilled in the art without departing from the main technical idea of the present invention.

Claims (18)

A step of sequentially stacking an oxide blocking film, a first insulating film, and a second insulating film on a semiconductor substrate; Selectively etching the first insulating film and the second insulating film to form a narrow opening and a wide opening; Forming a spacer on an inner wall of the opening; Forming a narrow trench and a wide trench by etching the semiconductor substrate using the spacer as a mask; Thermally oxidizing the inside of the trench to form a first thermal oxide film, thereby filling the inside of the narrow trench and partially filling the inside of the wide trench; Filling a portion of the inside of the wide trench filled with the first thermal oxide film with a first material layer capable of oxidation; And forming a secondary thermal oxide film by oxidizing an upper portion of the first material layer. The method of claim 1, wherein the narrow opening has a width of 0.5 μm and the wide opening has a thickness of 0.9 μm. The method of claim 1, wherein a space between the spacers formed on the inner wall of the narrow opening is 0.3 μm, and a space between the spacers formed on the inner wall of the wide opening is 0.6 μm. . 4. The method of claim 3, wherein a thickness of the first thermal oxide film in the narrow trench and the wide trench formed by using the spacer as a mask is 1000 kPa or more. 5. The method of claim 4, wherein the thickness of the second thermal oxide film in the wide trench is about 1000 to 1500 microns. The device isolation method of claim 5, wherein the device isolation region formed by filling the narrow trench is 0.35 μm, and the device isolation region formed by filling the wide trench is about 0.8 μm. 7. The method of claim 6, wherein the device isolation region is applied to a 64Mb semiconductor memory device. The method of claim 1, wherein the narrow opening has a width of 0.4 μm and the wide opening has a thickness of 0.6 μm. 9. The method of claim 1 or 8, wherein the spacing between the spacers formed on the inner wall of the narrow opening is 0.1 mu m, and the spacing between the spacers formed on the inner wall of the wide opening is 0.4 mu m. . 10. The method of claim 9, wherein a thickness of the first thermal oxide film in the narrow trench and the wide trench formed by using the spacer as a mask is 1000 GPa or more. The device isolation method of claim 10, wherein the device isolation region formed by filling the narrow trench is 0.25 μm, and the device isolation region formed by embedding the wide trench is about 0.5 μm. 12. The method of claim 11, wherein the device isolation region is applied to a 256Mb semiconductor memory device. The method of claim 1, wherein the oxide blocking film is formed by forming an oxynitride silicon in a thickness of about 240 GPa. 2. The method of claim 1, wherein the first insulating film is formed by forming silicon nitride in a thickness of about 1500 kPa. The method of claim 1, wherein the second insulating film is formed by forming HTO with a thickness of about 1000 GPa. The device of claim 1, wherein the spacer is formed by forming silicon nitride on the entire surface of the resultant after the opening is formed, and then performing anisotropic etching on the silicon nitride. Separation Method. The method of claim 1 or 15, wherein the second insulating film is removed after the trench forming process. 2. The method of claim 1 wherein the first material layer is polycrystalline silicon.