KR950001924B1 - N-bit recycling digital analogue converter - Google Patents

Abstract

The converter is designed to convert the high resolution signal and high speed signal utilizing N bit recycling. The converter comprises; the switching unit (101) inputting the M bit and K bit digital signal into a digital/analog converter; capacitors (C2,C3,C4) tuning the magnitude of the digital/analog converter output; a first analog signal subtracter (103); a second analog signal subtracter (104) outputting the charged analog signal after adding the output of the first subtracter (103); a switches (SW11,SW12) connected with the second subtracter.

Description

N-Bit Recycling Digital-to-Analog Converter

1 is a circuit diagram of a conventional analog-to-digital converter.

2 is a circuit diagram of an N-bit recycling digital-to-analog converter of the present invention.

3 is an output waveform diagram of a first analog signal subtracting unit in FIG. 2;

* Explanation of symbols for main parts of the drawings

101: switching unit 102: digital-to-analog converter

103: primary analog signal subtraction unit 104: secondary analog signal subtraction unit

OP1, OP2: Amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital-to-analog converters and, more particularly, to N-bit recycling digital-to-analog converters, which are fast and suitable for high resolution signal processing.

As shown in FIG. 1, the circuit of the conventional digital-to-analog converter receives first and second digital signals of N bits and NM bits, respectively, and converts the digital signals into N bits of binary data and outputs them. It is connected in the same manner as the decoder (1) (2) and 2 ⁿ reference resistors across the reference voltage (V _REF ＂H＂, V _REF ＂L＂) and switches according to the decoding output of the first decoder 1. A first switching unit 3 for outputting an analog voltage based on a reference resistance, first and second buffer amplifiers 4 and 5 for receiving and buffering an output signal of the first switching unit 3, and A second to switch the output of the first and second buffer amplifiers 4 and 5 by switching the analog voltage determined by the fine resistor strings R21 to R2n according to the decoding output of the second decoder 2. A third buffer for outputting an analog signal obtained by buffering the switching section 6 and the switching output of the second switching section 6 to an appropriate level. Consists of aeration (7).

As an example of converting a digital value into an analog in the conventional technique configured as described above, digital data of the upper M bits is input to the first decoder 1 among the N-bit inputs, and digital data of the lower (NM) bits is input to the second decoder. When input to (2), respectively, this decoder (1) (2) converts N-bit binary data to output 2 ⁿ decoded signals.

The reference voltage across the _{(V REF "H", V} REF "L") analog voltages determined respectively by the reference resistance (R11 ~ R1n) with 2 ⁿ of step (Step), depending on the voltage of the first switching unit (3 Is applied to the switch terminal.If only the switch of point A, which is a portion corresponding to the input code, is turned on by the signal decoded by the first decoder 1, the analog voltage by the resistors R11 and R12 is turned on. It is input to the first buffer amplifier 4 through a switch. Thereafter, the voltage at point A is automatically switched on and the analog voltage generated is input to the second buffer amplifier 5.

In this way, a reference voltage is generated in the micro-resistance strings R21 to R2n with the voltage obtained by buffering and amplifying the first and second buffer amplifiers 4 and 5 at a suitable level. At this time, the digital signal of the lower (nm) bit is decoded by the second decoder 2 to turn on a switch corresponding to the ⓒ part of the fine reference resistor, so that the voltage of the micro resistance string is input through the second switching unit 6. When the third buffer amplifier 7 is output, the analog voltage Vout buffered and amplified by the amplifier 7 is output.

However, in the case of the digital-to-analog converter operating as described above, two 2 ⁿ resistance strings are required to decorate two N-bit stages (STEP), which makes it difficult to match many resistance lines in a semiconductor process. In addition, since 2 ⁿ × 2 switches are required, the chip size increases, digital noise flows into the analog part, and digital switching noise appears at the analog output. Also, different buffer amplifiers (4) and (5) are used. There is a problem that the offset of the buffer amplifier is displayed as it is the offset of the output.

Therefore, in order to solve such a conventional problem, the present invention recycles N bits to reduce the size of the chip, and the upper and lower bit sections that can be generated in the amplifier by using one amplifier in the first analog signal processing. An N-bit recycling digital-to-analog converter has been devised to reduce the offset of P and to facilitate matching, which will be described below in detail with reference to the accompanying drawings.

2 is a circuit diagram of the N-bit recycling digital-to-analog converter of the present invention. As shown therein, the digital signal is recycled to the digital-to-analog converter 102 by dividing the digital signal into two steps, the upper part of M bits and the lower part of K bits. Amplification is performed through the capacitors C2, C3, and C8 for the switching unit 101 for switching the input, and the analog signal primarily converted by the digital-analog conversion unit 102, and an amplifier The primary analog signal subtraction unit 103 to be charged and processed through the primary analog signal subtraction unit 103 for the analog signal secondaryly converted by the digital-analog conversion unit 102 is processed. Secondary analog signal subtractor 104 adds the output signal and the analog signal charged and processed primarily to output the analog output signal.

Referring to the operation and effects of the present invention configured as described above in detail.

For example, a 16-bit digital-to-analog converter, which is an 8-bit recycling, will have two digital inputs divided into 2N bits. It is controlled by the second signal as an input group and input to the digital-analog converter 102. First, the switches SW1 to SW8 are connected to the digital data d0 to d7 by the first switch control signal. Is input to the digital-analog converter 102, the digital-analog converter 102 converts the analog signal to a lower 8-bit digital data value.

The signal converted into analog through the digital-analog converter 102 is switched on by the switch SW10 of the primary analog signal subtractor 103 to adjust the amplitude through the capacitors C2, C8 and C3. The amplitude adjustment to be.

The amplitude-adjusted signal is transmitted to the secondary analog signal subtraction unit 104. At this time, the switch state of the secondary analog signal subtraction unit 104 is SW11 and SW11 'are turned on and SW12 and SW12' are turned off. The amplitude-adjusted signal in the analog signal subtractor 103 is charged with Va in the capacitor C19 through the path of the switch SW11-> capacitor C19-> switch SW11 '-> ground GND.

In this state, when the second switch control signal comes, the switches SW11 to SW8 of the switching unit 101 are connected to the digital data bits d8 to d15, so that the digital data corresponding to the lower bits d8 to d15 is obtained. When the analog signal corresponding to the analog signal is changed and output through the digital-to-analog converter 102, the switch SW10 of the primary analog signal subtractor 103 is turned off and C2 / C3 = 1 to convert the converted voltage. (Vb) is sent to the secondary analog signal subtraction unit 104.

At this time, as the switch state of the secondary analog signal subtractor 104 is switched off, SW11 and SW11 'are turned off, and SW12 and SW12' are turned on. Will appear.

As a result, when recycled in half with respect to the input digital data input, the output is as follows.

As described above, when a digital input such as FIG. 3a is recycled and input to the digital-analog converter 102, an analog signal as shown in FIG. 3B, which is converted through the digital-analog converter 102, is output. When C2 / (C3 + C8) = 1/4 and C2 / C3 = 1 in the signal subtractor 103, the voltage Vb output from the primary analog signal subtractor 103 is as shown in FIG. 3C. same.

When the 8-bit digital-to-analog converter is configured as a current source type, the current source requires 255 current sources. However, in the present invention, only 16 are required so that the circuit size is significantly reduced, and the same digital-to-analog converter is required. Recycling is used to reduce the offset errors of the upper and lower bit groups.

As described in detail above, the present invention accepts an upper or lower N-bit input signal from a 2N bit digital input signal to the first switch control signal and then lowers or uppers the primary and secondary switch control signals after digital / analog conversion. By taking an input signal of K bits and outputting it as an analog output signal after digital / analog conversion, the offset error of the upper and lower bit groups is reduced.

Claims (4)

A switching unit 101 for dividing the digital signal into two steps of an upper M bit and a lower K bit so as to be recycled to the digital-analog converter 102, and the digital-analog converter 102 The first analog signal subtractor 103 for amplitude adjustment through the capacitors C2, C3, C8 for the primary signal converted in the < RTI ID = 0.0 >) < / RTI > The analog signal converted by the conversion unit 102 is added to the output signal processed through the primary analog signal subtraction unit 103 and the analog signal charged and processed primarily to output an analog output signal. And a secondary analog signal subtractor (104). The method of claim 1, wherein the first analog signal subtraction unit uses the amplifier OP1 with the amplification degree of the first control signal as C2 / (C8 + C3) and the amplification degree with the second control signal as C2 / C3. An N-bit recycling digital-analog converter characterized by reducing the area of a semiconductor chip by firstly dividing the amplification degree as a whole by amplifying the converted upper bits and lower bits. The capacitor C2 of claim 1 or 2, wherein the primary analog signal subtractor is connected to the output of the digital-analog converter 102, and the capacitor C8 connected in series with the capacitor C8 and the switch SW10 connected in series. The output terminal of the amplifier OP1 connected to the connection point of C3) and to the inverting terminal (-) and the ground resistance R9 of the amplifier OP1 and the non-inverting terminal (+) connected to the ground side is connected in parallel. A N-bit recycling digital-analog converter, characterized in that the first-order secondary digital-analog conversion amplification degree is changed by selectively changing the amplification degree by the connection point of the capacitor C3 and the switch SW10 to the switch. The secondary analog signal subtraction unit 104 has an output terminal of the primary analog signal subtraction unit 103 connected to the inverting terminal (-) of the amplifier OP2 through the switches SW11 and SW12. Connected to the non-inverting terminal (+) of the amplifier OP2 through the switches SW12 and SW11 ', and the connection points of the switches SW11 and SW12 and the switches SW12 and SW11'. A capacitor (C19) is connected in parallel between the connection point of the N-bit recycling digital-analog converter, characterized in that the output terminal of the amplifier (OP2) is fed back through the capacitor (C20) is connected to the inverting input terminal.