KR950000667B1 - Band limit signal generator without isi & jitter - Google Patents

Abstract

The signal generator providing the band limited jitter free signal by excluding the mutual interference in low speed random digital signal transmission comprises a control signal generator (1) generating the control signal by comparing the NRZ digital input data string with the previous data string; a signal generator (3) providing DC signal which corresponds to the AC output signal of the control signal generator (1); an output selector (2) having four bidirectional analog switches to select one of the signals from the control signal generator (1) and the signal generator (3).

Description

Band-limited signal generator without cross-signal interference and jitter

1 is a block diagram of a band limit signal generator according to the present invention;

2 is an input / output signal waveform diagram for explaining the present invention.

3 is a detailed configuration diagram of the present invention.

4 is a signal waveform diagram of a control signal generation circuit.

5 is an input / output signal spectrum diagram showing bandwidths of band-limited and non-band-limited signals.

* Explanation of symbols for main parts of the drawings

1: control signal generation circuit 2: output selection circuit

3: Waveform and signal generating circuit U1, U2, U3: D flip flop

U4, U5: Exclusive OR gate U6, U7, U8: Inverter

U9, U10, U11, U12: AND gate U13: 4-D flip flop

U14: 4-bidirectional switch

The present invention relates to a cross-signal interference and jitter-free band-limited signal generator to reduce bandwidth spreading that occurs in transmission of random low-speed digital signals.

In general, since the actual transmission channel has a limited bandwidth, the transmitted pulse tends to spread during transmission. This spreading overlaps with an adjacent signal, causing distortion of intersymbol interference (IS1). In addition, jitter due to inter-signal interference occurs, which greatly affects the probability of signal attenuation or error in a real system.

One way to control jitter and cross-talk interference is to make the outgoing pulse an appropriate waveform. It is known until recently that it was designed to reduce side waves while simultaneously solving jitter and cross-talk interference problems.

However, the known method uses a feedback loop for comparison between an input signal sequence and an output signal, and there are problems such as unstable elements occurring in circuit fabrication and the use of many clocks.

Therefore, the present invention devised to solve the above problem does not return the output signal to the input for comparison with the input signal, and the interference between the interference and jitter problem while reducing the unstable factor of the circuit fabrication and the clock usage, etc. While simultaneously solving the problem, there is provided a band limiting signal generator capable of band limiting.

In order to achieve the above object, the present invention provides a control signal generating means for generating a control signal by receiving random low-speed non-return to zero (NRZ) digital input data and a clock pulse from the outside, and supplying a clock pulse from the control signal generating means. The waveform and the signal generating means for receiving the DC level signal of the sinusoidal wave and the control signal supplied from the control signal generating means and the control signal generating means connected to the control signal generating means. It consists of an output selection means for selecting only one of the signals generated and supplied and outputting it as a final output signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a band limit signal generator according to the present invention, where 1 is a control signal generation circuit, 2 is an output selection circuit, and 3 is a waveform and signal generation circuit, respectively.

The band limiting signal generator according to the present invention is composed of a control signal generating circuit 1, an output selecting circuit 2, and a waveform and signal generating circuit 3 as shown in FIG.

The control signal generation circuit 1 is connected to an external input signal terminal and a clock pulse terminal to latch an input random NRZ digital signal at a timing by a clock pulse having an appropriate external binary waveform. The result of the comparison between the previous input signal (already input signal of 1 bit interval) and the current input signal is generated as a control signal.

The output selection circuit 2 is connected to the control signal generation circuit 1 and the waveform and signal generation circuit 3 to generate the control signal generation circuit among DC levels of the sine wave output from the waveform and signal generation circuit 3. By the control signal pulse generated in (1), only one output signal of the waveform and the output of the signal generation circuit 3 is finally outputted. Here, the switching time for output selection of the output selection circuit 2 should be 1 bit interval.

The waveform and signal generation circuit 3 is composed of a bandpass filter composed of an operational amplifier (Op Amp) and connected to the control signal generation circuit (1) to receive an output clock pulse of the control signal generation circuit (1) to receive a sine wave. Sin2πfT and -Sin2πfT, respectively, and generate a positive DC level signal and a negative DC level signal, which are at the same level as the peak value of a sine wave, and output the signal to the output selection circuit 2. Will be released. Here, the waveform and signal generation circuit 3 may be configured by any method, but the generated DC level should be equal to the peak value of the sine wave generated so that the waveform of the final output signal is continuous and flat.

An external random NRZ digital input signal and a clock pulse are input to an input signal terminal of the control signal generation circuit 1, and the control signal generation circuit 1 outputs a comparison result between the input digital input signals as a control signal and an output selection circuit. Inputted to the input signal terminal of (2), the output selection circuit 2 outputs the output signal of the waveform and signal generation circuit 3 as the final output at a switching time of one bit interval. That is, when the data bit already input in the digital input signal string is "0" (LOW) and the currently input data bit is "1" (High), the control signal generated by the control signal generation circuit 1 causes the The sinusoidal wave of Sin2? FT of the waveform and the signal generating circuit 3 is output, and is continuously connected to the waveform already output at intervals of 1 bit.

If the input data bit is "1" and the current input data bit is "0", the sinusoid of -SinπfT is positive, and if both bits are "1", the positive DC level is two bits. If all are "0", negative DC level leads to final output, respectively.

2 is an input / output signal diagram illustrating a band limit signal generator according to the present invention.

The output waveform is a band limited, i.e. filtered signal for a random NRZ digital input signal. The high frequency component of the portion where a transition from "1" to "0" or "0" to "1" occurs in the digital input signal sequence is a sine wave having a continuous and flat slope according to the operation described in FIG. Since it appears to be filtered by the component, the band limit signal, which is the object of the present invention, is eventually generated.

FIG. 3 is a circuit diagram showing the detailed configuration of the band limiting signal generator according to the present invention. FIG. 4 is a signal waveform diagram of the control signal generating circuit 1 of FIG. 1, where U1, U2 and U3 are D flip-flops, U4, U5 are exclusive UN gates, U6, U7, U8 are inverters, U9, U10, U11, U12 are AND gates, U13 are four D flip-flops, and U4 are four bidirectional analogs forming the output selector circuit (2). A switch, and 3 denotes a bandpass filter as a block of the waveform and signal generator 3 of FIG.

In the control signal generation circuit 1 according to the present invention, as shown in FIG. 3, random NRZ digital input data is applied to the data input terminal D1 and an external input clock pulse is connected to the clock input terminal CP1. The flip-flop U1, the output terminal Q1 of the D flip-flop U1 is connected to the data input terminal D2, and the D flip-flop U2 and the inverted output terminal whose external input clock pulses are connected to the clock input terminal CP2. Q3) is connected to the data input terminal D3 and the clock pulse is connected to the clock input terminal CP3, the D flip-flop U3, the output terminal Q1 of the D flip-flop U1, and the D flip-flop U2. Exclusive OR gate U4 connected to an output terminal Q2, an exclusive OR gate U5 connected to an output terminal Q1 of the D flip-flop U1 and an output terminal Q3 of the D flip-flop U3, and the exclusive OR AND gate U9 connected to the output terminal of the gate U4 and the exclusive OR gate U5, the exclusive OR gate U4 and the exclusive OR gate U5 AND gate U10 connected to the output terminal via an inverter U8, AND gate U11 connected to an output terminal Q1 of the D flip-flop U1 and an output terminal of the exclusive OR gate U4 through an inverter U7. An AND gate U12 connected to an inverted output terminal / Q1 of the D flip-flop U1 and an output terminal of the exclusive OR gate U4 through an inverter U7, and the AND gates U9, U10, U11, Four D flip-flops (U13) for connecting data input terminals A1, A2, A3 and A4 to the output terminals of U12) and inputting external input clock pulses to the clock input (CP4) through the inverter U6. It consists of.

In the output selection circuit 2 according to the present invention, as shown in FIG. 3, the output control signals Y1, Y2, Y3, Y4 of the control signal generation circuit 1 are input terminals C1, C2, C3, Four connected to the data input terminals A, B, C, and D, respectively, connected to C4) and output waveforms and signal terminals S1, S2, S3, and S4 of the waveform and signal generation circuit 3 of FIG. It consists of an analog bidirectional switch.

The waveform and signal generation circuit 3 according to the present invention is composed of a generator connected to the output terminal Q3 of the D flip-flop U3 to generate a sinusoidal wave of Sin2πfT and -Sin2πfT, a positive DC level and a negative DC level. do.

Referring to Figure 4 describes the detailed operation of the present invention.

The external digital input data is input to the D flip-flop U1 of the control signal generation circuit 1 in the form as shown in FIG. 4 (I), and output when a rising transition occurs at the external input clock pulse terminal CP1. Q1 is in a logic " 1 " state and is input to the data input terminal D2 of the D flip-flop U2, the exclusive OR circuits U4 and U5, and the input terminal of the AND gate U11. The inverted output / Q1 of the D flip-flop U1 is in a logic " 0 " state and is input to the input terminal of the AND gate U12. When the rising transition of the clock pulse occurs at the clock pulse input terminal CP2 of the D flip-flop U2, the output of the D flip-flop U2 becomes a logic " 1 " state and is output to the exclusive OR gate U4.

The output Q3 of the D flip-flop U3 becomes a logic " 0 " state when a rising transition occurs at the input clock pulse terminal CP2, and is output to the input terminal of the exclusive OR gate U5, the waveform, and the signal generator. . The state " 1 " which is the output Q1 of the D flip-flop U1 and the state of the output Q2 of the D flip-flop U2 are input to the exclusive OR gate U4, and the result is exclusively ORed. The exclusive OR gate U5 outputs the results of the outputs Q1 and Q3 of the D flip-flop U1 and the D flip-flop U3.

The outputs of the exclusive OR gates U4 and U5 are input to the AND-gate U9 to be logically output, and the AND gates U10, U11 and U12 respectively output logical results in the same manner. When the output of each AND gate is input to four D flip-flops U13, and a rising transition occurs at the input clock pulse terminal CP4 that is generated and input from the interleaver U6, the four D flip-flops U13 The state of the input terminal is released to each output terminal (Y1, Y2, Y3, Y4) as it is. Accordingly, the control signal generation circuit 1 compares the level of the previous data and the currently input data in the digital input data signal string and sends them out as control signal pulses. This operation is continuously performed while the digital input signal is continued to continue the control signal. Will print.

The control signal generation circuit 1 uses the input clock pulse terminal CP4 of the four D flip-flops U13 in order to output the selected waveform at the correct time, which is valid for low-speed random NRZ digital input data. .

The output selection circuit 2 includes output signals Y1, Y2, Y3, and Y4 of the control signal generation circuit 1 connected to input signal terminals C1, C2, C3, and C4, and the waveform and signal generation circuits. The output signals S1, S2, S3, S4 of (3) are connected to the input signal terminals A, B, C, and D to generate the waveforms and signals according to the output control signal pulses of the control signal generation circuit 1. Only one output signal of the circuit 3 is sent out. When the control signal pulse of the output terminal Y1 of the control signal generation circuit 1 is "1", Sin2πft which is a waveform of the waveform and the signal waveform of the output terminal S1 of the signal generation circuit 3 is converted into the output terminal Y2. If the control signal pulse is "1"-Sin2πfT, if the control signal pulse of the output terminal Y3 is "1", the positive DC level is set. If the control signal pulse of the output terminal Y4 is "1", the negative DC level is respectively set. Will be sent.

At this time, in order to maintain the continuity and flatness of the output signal waveform, it is necessary to make a connection with the waveform already output with the accurate switching time of 1 bit interval.

5 shows the spectrum of the random NRZ digital input data A and the output signal B of the band limit generator according to the present invention, which is clearly limited in bandwidth.

Accordingly, the present invention, which is constructed and operated as described above, is applicable to communication devices and data communications in which the bandwidth of a transmission path is limited, and reduces the spread of bandwidth generated in the transmission of random low-speed digital input signals. The jitter problem can be solved at the same time, so there is no feedback circuit and stable operation is possible.

Claims (5)

In the band limiting signal generator, a control signal generating means (1) for generating a control signal pulse by comparing a level between a current input data and a previous input data in an external random low-speed NRZ digital input data stream, and generating the control signal. Positive DC level and negative DC connected to the means 1 to receive the output clock pulse of the control signal generating means 1, which is at the same level as the peak value of the sine wave and the sine wave. A waveform and signal generating means 3 for generating a level signal, and connected to the control signal generating means 1 and the waveform and signal generating means 3 to receive a control signal pulse of the waveform and signal generating means 3. And an output selecting means (2) which selects one of the outputs and outputs the final output, thereby limiting the bandwidth spread of the input random low-speed NRZ digital data to be free from cross-sign interference and jitter. Reverse limit signal generator. The first D flip-flop (U1) according to claim 1, wherein the control signal generating means (1) has random NRZ digital input data applied to an input terminal (D1) and an external input clock pulse connected to a clock input terminal (CP1). And a second D flip-flop U2 connected to an output terminal Q1 of the first D flip-flop U1 connected to a data input terminal D2 and an external input clock pulse clocked to CP2, and the external input clock. A third 3D flip-flop U3 and an output terminal Q1 of the first D flip-flop U1 and the second D flip-flop having a pulse connected to a clock input terminal CP3 and an inverted output terminal / Q3 connected to a data input terminal D3. An output terminal Q3 of a first exclusive OR gate U4 connected to an output terminal Q2 of U2, an output terminal Q1 of the first D flip-flop U1, and an output terminal Q3 of the third D flip-flop U3. DP connected second exclusive OR gate U5, first AND gate U9 connected to an output terminal of the first exclusive OR gate U4 and the second exclusive OR gate U5, and the first The second AND gate U10 connected to the output terminal of the exclusive OR gate U4 and the second exclusive OR gate U5 through the first inverter U8, the output terminal Q1 of the first D flip-flop U1, and the The third AND gate U11 connected to the output terminal of the first exclusive OR gate U4 through the inverter U7, the inverted output terminal / Q1 of the first D flip-flop U1, and the first exclusive OR gate U4. Data input terminals A1, A2, A3, and A4 at the output terminals of the fourth AND gate U12 and the first to fourth AND gates U9, U10, U11, and U12 connected to the output terminal of the fourth AND gate U12. And each of the four D flip-flops (U13) connected to each other and inputting an external input clock pulse through a third inverter (U6) to a clock input terminal (CP4). 2. The band limit signal generator according to claim 1, wherein the waveform and signal generating means (3) comprise a bandpass filter composed of an operational amplifier (Op Amp). 2. The band limit signal generator as claimed in claim 1, wherein the output selecting means (2) consists of four analog bidirectional switches. 3. The method of claim 2, wherein the waveform and the waveform of the signal generating means (3) are generated by using the output signal of the output terminal (Q3) of the D flip-flop (U3) of the control signal generating means (1). Band limited signal generator, characterized in that.