KR950000426B1 - Non-volatile memory device with error correcting circuit of plural byte unit - Google Patents

Abstract

The memory (EEPROM) comprises a memory bit loading means for storing memory bits inputted as a byte unit in page buffers of a first group, a parity extractor for receiving the stored memory bits as the unit of certain bytes to generate some parity bits, a parity loading means for storing some parity bits in page buffers of a second group, a program section for writing simultaneously in the selected cells of memory array and parity cell, a write parity extractor for generating a write parity, and an error correcting circuit for comparing memory data bits with parity bits.

Description

Nonvolatile Memory Device with Multiple Fault Incorrect Circuits

1 is a conventional embodiment

2 is another conventional embodiment

3 is a block diagram according to the present invention.

4 is a diagram illustrating a memory array of FIG. 3

5 is a schematic diagram showing a light process according to the present invention.

6 is a schematic diagram showing a lead process according to the present invention.

7 is an internal configuration diagram of a parity generator used in the present invention.

8 is an operation timing diagram according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a wrong correction circuit in units of multiple bytes capable of random writing.

Error check and correction circuits (ECCs) for checking and correcting defects in memory cells are generally used to improve the reliability and yield of memory devices. When using an error correction circuit of one byte, a parity cell corresponding to 50% of the memory cell is required, and there is a problem in that the chip size increases as the memory is highly integrated. In order to overcome this problem, it is necessary to reduce the ratio of parity cells to memory cells by using error correction circuits in units of multiple bytes instead of single bytes, for example, 4 bytes and 8 bytes. However, when an error correction circuit is used for a multibyte unit, a set of data corresponding to a unit byte must be sequentially input and write operation must be performed at the same time.

An example of a conventional nonvolatile memory device using the above error correction circuit in units of one byte is shown in FIG. The Y pyrom shown in FIG. 1 is a system capable of error search and correction in units of 1 byte (12 bits) composed of 8 bits of data and 4 bits of parity. Referring to FIG. 1, eight bits of data input through the data input buffer are loaded into the memory array 11 together with four bits of parity data generated by the parity generator. One byte of data (including parity data) stored in the memory array 11 is transmitted through the sense amplifier 12. If an error occurs in the data passing through the sense amplifier 12, it is searched and corrected through the paths to the parity generator 13, the parity decoder 14, and the exclusive oragate 15.

In such an error correction circuit, since the parity bits are 50% of the data bits, the chip size and increase are inevitable due to the increase in the number of parity bits as the number of data bits increases.

In order to solve the problem shown in the error correction circuit of FIG. 1, a ROM (ROM) that performs error correction in units of a plurality of bytes is shown in FIG. This is disclosed in Korean Patent Publication No. 90-4812 (Applicant: Hitachi, Date of Priority: February 15, 1982). In the patent, if the error correction is performed in units of a plurality of bytes, for example, in units of 4 bytes, the parity data is 6 bits, which requires 18.8% parity cells for 32 bits (4 bytes). As a result, as in the second diagram, in the error correction circuit of a multi-byte unit, as the size of the unit byte increases, the amount of required parity cells decreases, so that the increase in chip size can be suppressed.

However, since the relative number of parity cells is small, the correction efficiency is lower than that of one byte (FIG. 1). The reason for this is that as in the case of FIG. 1, in the error correction correcting circuit in one byte unit, one bit per 12 bits (8 data buffers + 4 parity bits) can be corrected, but as in the case of FIG. This is because the error correction circuit corrects one bit per 38 bits (32 data bits + 6 parity bits). In the ROM of FIG. 2, 38 memory cells (including parity cells) are simultaneously selected by the output signal of the X decoder and the Y decoder, and the read operation is performed. Bit data signals are sequentially transmitted to the external terminals DC0 to DC7 four times.

As described above, in the ROM performing only a read operation, even if error correction is performed in units of a plurality of bytes, after decoding the column in units of 4 bytes, a sense amplifier decoding for selecting 1 byte corresponding to the selected address from the 4 bytes is performed. There is no difficulty in error correction and lead operation. That is, since the memory array and the parity array of FIG. 2 are composed of nonvolatile ROM cells, the above-described error correction operation is not affected whether the data is randomly stored or temporarily stored.

However, in the case of using a multi-byte error correction circuit in an electrically erasable and programmable ROM, that is, an EEPROM, the correct parity bit must be written only when multiple bytes are simultaneously written and data is input in order. Is generated, there is a constraint that data cannot be written randomly.

Accordingly, an object of the present invention is to provide a device capable of enabling an error correction operation in units of a plurality of bytes even when input data is randomly input in EPI.

Another object of the present invention is to provide an apparatus capable of randomly writing input data in an EPROM having an error correction circuit of a plurality of bytes.

In order to achieve the object of the present invention, the YPIROM device according to the present invention temporarily stores externally input data in byte units in page buffers in a memory cell array, and then stores them in a parity generator in units of multiple bytes. The parity bits corresponding to the data bits of the multi-byte unit are temporarily stored in the page buffers of the parity cell array. The data bits and parity bits stored in the page buffers are then written to the memory cell array and the parity cell array, respectively, in program mode. The configuration of the present invention required for this is, the memory bit loading means for storing the memory bits of the byte unit in the page buffer of the memory cell array, and the predetermined number of parity by inputting the memory bits stored in the page buffers in plural byte units Parity extraction means for generating bits, parity bit loading means for temporarily storing the parity bits in the page buffers of the parity cell array, data bits and parity stored in the page buffers of the memory cell array and the parity cell array. Program means for writing bits to said cell arrays. The data read from the memory cell array is corrected and read by the error correction decoder and the corrector.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 3 shows a schematic configuration of Ypyrom according to the present invention.

The memory array 100 shown in FIG. 3 is assumed to have a capacity of 1M bits composed of 1024 pages (1 page = 128 bytes = 1 jbit). In the present invention, an embodiment is applied to the case of error correction in units of 4 bytes. Each page is selected by the low address buffer 130 and the low decoder 140. The first color address buffer 150 and the first column decoder 160 that input the first column address YAi control the column gate 120 such that each byte is selected in units of 4 bytes in each page. The second column address buffer 310 and the second column decoder 290 inputting the second column address YBi select one byte from among the four bytes first selected by the first column decoder 160. The page buffer 110 is composed of latches respectively connected to respective column select transistors (not shown in FIG. 3) constituting the column gate 120 through respective bit lines, and temporarily input data. To play a role. The data input buffer 280 and the data output buffer 250 convert the input and output external and internal data into the CMOS level and supply them to the internal and external.

Note that the address buffers, decoders, page buffers, column gates, and data input / output buffers are elements that are basically embedded in a typical EPI device. The parity generator 200, the error correction decoder 230, and the corrector 220 are basic elements constituting the error correction circuit.

The parity generator 200 generates 6-bit parity bits used for error correction in units of 4 bytes. The error correction decoder 230 inputs the six bits of parity bits to supply data (32 bits) corresponding to the position of the defective cell to the collector 220. Meanwhile, the input data selector 270 for inputting 8-bit input data from the data input buffer 270 selects one byte out of four bytes according to the information output from the second column decoder 29. ). The parity selector 300 transmits 6-bit parity data generated by the parity generator 200 to the page buffer in the parity cell array. The parity sense amplifier 400 reads 6-bit parity data loaded in the page buffer 110, and the internal column address generation circuit 170 stores parity data of each set (4 bytes) in the page buffer corresponding to the selected address. An address is automatically generated for loading and supplied to the first column decoder 160 and the parity selector 300.

4 shows an example of the configuration of the memory cell array 100 shown in FIG. The pages 101 to 111 divided into blocks are divided based on the input / output unit. That is, since one input / output unit is 8 bits, the memory data is 32 bits (4 bytes). When the corresponding 6-bit parity data is added, a total of 38 bits is one set. Since one page is composed of 128 bytes, it can be seen that one page is composed of 32 sets. Each page has a capacity of 1K bits (1024 bits). Therefore, when the memory cell array is constructed in this manner, the parity data required for one page (128 bytes, 32 sets) is 32 x 6 = 192 bits, and as shown in FIG. Two parity cell arrays 105 and 111 composed of bits may be disposed. Since one page is composed of 32 sets (128 bytes = 4 bytes x 32), it can be seen that 32 times of parity data generation cycles are operated for 6 bits every cycle in order to error correct one page.

5 is a view for explaining the writing process performed in the error correction mode according to the present invention. In FIG. 5, the page buffer 110, the first column decoder 150, the column gate 120, the page selector 300, the parity sense amplifier 400, the page sense amplifier 500, and the sense amplifier 270 are illustrated. The input data selector 270, the data input buffer 280, and the parity generator 200 are used, and their implementation circuits are revealed. S1, S2, S3, S4, S5, and S6, which are outputs of the parity generator 200, represent 6-bit parity data. There are 32 data lines DL1-DL32 carrying memory data and six parity lines PL1-PL6 carrying parity data. Like the memory cell arrays 101, 102, 103, and 104, the parity cell array 105 includes page buffers 110 connected to respective bit lines. Since the internal structure of the parity cell array 105 is the same as that of the memory cell array, it is not shown. The memory cell (or parity cell) is selected by the word line WL and the string selection line SL, and the page buffer 110 and the selected bit line are connected by the bit line selection signal SBL. The signal YD in the first column decoders 160a, ..., 160d causes the column address signals Pi, Qi and Ri to be output with valid values.

The control signals LD, LCHfa, YW1, LCHfd and the like shown in FIG. 5 may be made from the control circuit 180 of FIG. 3, which is a signal used in a known Y pyrom.

6 is a schematic diagram illustrating a lead process performed in the error correction mode according to the present invention. As shown, the internal configuration of the error correction decoder 230, the collector 220, the sense amplifier decoder 240 and the data output buffer 250 is shown.

7 shows the internal structure of the parity generator 200 used in the present invention. The inputs of the logic combination circuits 201, ..., 206, which are composed of exclusive oragates and generate respective parity bits S1, S2, S3, S4, S5, and S6, are read from the parity cell array 105. 6 bits of parity data and 32 bits (4 bytes) of memory data read out from an arbitrary selected page 101 of the memory cell array 100. The 6-bit parity data is supplied to the parity selector 300 and the error correction decoder 230, as shown in the fifth and sixth degrees.

FIG. 8 is a timing diagram illustrating the write operation of the present invention based on the above FIG. 5. FIG. In the write operation for error correction, 128-byte data corresponding to one page is temporarily stored in each page buffer 110 connected to each bit line of the memory cell array 100 according to address selection. The data loading period Td1 and the memory data temporarily stored in the page buffer 110 are inputted from the parity journaler 200, and 6-bit parity data S1,..., Corresponding to each group (4 bytes, 32 bits) are input. A parity generation period Tpg for temporarily storing it in a parity page buffer connected to each bit line of the parity cell array 105 generating S6, and a program period Tpgm for writing data stored in the page buffer to a memory cell. Is done.

Next, an error correction operation according to the present invention will be described with reference to the timing diagram of FIG. In the following description, since the present invention enables writing in multiple byte units (e.g., 4 byte units) in EPIROM, it will be described in detail how an error correction operation is performed while reading and writing data in 4 byte units at the same time. Will be.

First, in the data loading period Td1, input data input through the data input buffer 280 is selected by one byte by the input data selector 270, and finally the input address by the first column decoder 160. It is loaded into the page buffer corresponding to As shown in FIG. 8, in response to 128 address transitions, 128 bytes of input data are randomly loaded into each page buffer (1 byte of input data is entered in one address transition). When all input data (128 bytes) corresponding to one page is loaded into the page buffer, it enters the parity generation period (Tpg). The parity generation period starts when the parity enable signal LD applied to the inverter of the parity selector 300 of FIG. 5 is transitioned to the "low" state. In this period, the internal column address is automatically generated by the internal column address generation circuit 170 corresponding to 32 sets of one page. As the signal YD, which enables the first column decoder 160 in response to the internal column address, becomes “high,” a set (4 bytes) of data are transmitted by the column gate 120 to the page sense amplifier 500. Is read through).

Here, in order for data stored in the page buffer 110 to be read by the page sense amplifier 500, in FIG. 5, the bit line selection signal SBL and the bit line discharge signal DCB are " high " and " low " "It is natural to be in a state. In this case, the word line does not affect the operation.

A set (4 bytes) of memory data read from the page sense amplifier 500 is input to the parity generator 200, and 6-bit write parity data corresponding to the input set of memory data is generated. . This 6-bit parity data is loaded into the parity page buffer of the parity cell array 105 in accordance with the corresponding address. As described above, the process of loading the parity data into the parity page buffer from the reading of a set of data loaded from the page buffer 110 of the memory cell array is repeated 32 times, thereby providing a data capacity of 32 trillion (128 bytes). The parity generation period for one page having is completed. Thus, input data and corresponding parity data are temporarily stored in the page buffer.

Here, the configuration of the memory cell array and the parity cell array is only different according to the information capacity, and the basic configuration is the same. In addition, it should be noted that the functions and configurations of the page buffers provided in these arrays are the same.

Then, in the program period Tpgm, input data and parity data temporarily stored in the page buffer are written to the selected memory cells of the memory cell array and the parity cell array, respectively, similarly to the normal program method. In other words, 1K bits (128 bytes) of input data and 192 bits of parity data are simultaneously written. In the read operation, in response to the selected address, the first column decoder 160 stores a set (4 bytes = 32 bits) of memory data and 6 bits of parity data, respectively, in the sense amplifier 210 and the parity sense amplifier 400. Read by the memory data and the parity data are input to the parity generator 200. The parity generator 200 generates 6-bit read parity data corresponding to the set of memory data and supplies the parity data to the error correction decoder 230. The output of the error correction decoder 230 is compared one-to-one at the exclusive or gate of the corrector 220 with the read memory data, and if any bit in the memory data is in an error state, Is corrected. Then, it is decoded by the sense amplifier decoder 240 controlled by the outputs YS1-YS4 of the second column decoder 290 of FIG. 3, and finally, the data of 1 byte selected through the data output buffer 250 is obtained. .

As described above, the present invention can generate parity data corresponding to input data in units of a plurality of bytes even when input data is randomly input, and simultaneously write and read the input data and the parity data to a cell array. There is an effect that the error correction operation can be performed in units of multiple bytes in EPIROM.

Claims (3)

An EPIROM having a memory cell array and a parity cell array, each having page buffers, comprising: memory bit loading means for storing memory bits input in byte units in a first group of page buffers, and the first group of pages Parity extracting means for inputting memory bits stored in the buffers in units of a plurality of bytes to generate a predetermined number of parity bits, and parity bit loading means for storing the predetermined number of parity bits in a second group of page buffers; And a plurality of bytes of memory bits and a predetermined number of parity bits stored in the first and second group of page buffers are simultaneously applied to the selected memory cells and the parity cells of the memory cell array and the parity cell array, respectively. Ipyrom characterized by being lighted. 2. The Epyrom according to claim 1, wherein the plurality of byte memory bits and a predetermined number of parity bits are read at the same time. 1. An iROM having a memory cell array and a parity cell array for inputting and outputting memory data in byte units, wherein the first and second groups of page furs are temporarily stored in the memory cell array and the parity cell array. Write parity extracting means for inputting the memory data from the page buffers of the first group into a plurality of byte units to generate write parity data corresponding to the memory data of the plurality of byte units; Parity loading means for storing in page buffers of a second group, and memory data and write parity data stored in the page buffers of the first and second groups at the same time to the selected cells of the memory cell array and the parity cell array. Program means and the parity cell array. Lead parity extracting means for inputting read write parity data to generate lead parity data, and simultaneously inputting the lead parity data and a plurality of bytes of memory data to convert the memory bits of the memory data into lead parity bits of the read parity data; Y pyrom, characterized in that it comprises an error correction means for comparing each.