KR940026947A - Bit line sense amplifier control signal precharge circuit - Google Patents

Bit line sense amplifier control signal precharge circuit Download PDF

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Publication number
KR940026947A
KR940026947A KR1019930009631A KR930009631A KR940026947A KR 940026947 A KR940026947 A KR 940026947A KR 1019930009631 A KR1019930009631 A KR 1019930009631A KR 930009631 A KR930009631 A KR 930009631A KR 940026947 A KR940026947 A KR 940026947A
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KR
South Korea
Prior art keywords
bit line
vcc
potential
precharge
sense amplifier
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KR1019930009631A
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Korean (ko)
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KR100265602B1 (en
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이재진
김태윤
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김주용
현대전자산업 주식회사
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Priority to KR1019930009631A priority Critical patent/KR100265602B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 디램소자의 비트라인 감지증폭기 제어신호의 프리챠지 전위를 비트라인 감지증폭기를 인에어블 시키지 않는 범위에서, RTO 신호의 프리챠지 전위는 전원전압 Vcc와 1/2(Vcc) 사이의 전위, /S 신호의 프리챠지 전위는 1/2(Vcc)와 그라운드 전압 사이의 전위가 되도록 회로를 구성하여 디램소자의 데이타 억세스 타임과 전력 소모를 줄인 비트라인 감지증폭기 제어신호 프리챠지 회로에 관한 기술이다.According to the present invention, the precharge potential of the RTO signal is a potential between the power supply voltage Vcc and 1/2 (Vcc) within a range in which the precharge potential of the bit line sense amplifier control signal of the DRAM device is not enabled. Of the bit line sense amplifier control signal precharge circuit which reduces the data access time and power consumption of the DRAM by configuring the circuit so that the precharge potential of the / S signal is 1/2 (Vcc) and the ground voltage. to be.

Description

비트라인 감지증폭기 제어신호 프리챠지 회로Bit line sense amplifier control signal precharge circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 비트라인 감지증폭기 제어신호 프리챠지 회로를 도시하는 회로도, 제4도는 본 발명의 셀 데이타의 리드 동작과 관련된 신호의 타이밍도.3 is a circuit diagram showing a bit line sense amplifier control signal precharge circuit of the present invention, and FIG. 4 is a timing diagram of a signal related to a read operation of cell data of the present invention.

Claims (2)

디램소자의 비트라인 감지증폭기 제어신호 프리챠지 회로에 있어서, 비트라인 감지증폭기 제어신호인 RTO, /S의 프리챠지 전위를 RTO 신호는 1/2(Vcc)와 Vcc 사이의 전위로 유지시키고, /S는 1/2(Vcc)와 Vss 사이의 전위로 유지시켜 데이타 엑세스타임과 전력 소모를 줄이기 위하여, 더미셀 A와, 유사 비트라인 B와, 더미셀을 제어하기 위한 더미워드라인과, 상기 유사 비트라인 B를 프리챠지시키기 위한 프리챠지 회로 G와, 드레인이 상단 더미셀의 유사 비트라인인 노드 N31에 접속되고 게이트가 프리챠지 동작시 로직하이 상태를 일정시간 유지하는 S1 신호에 의해 제어되어 상단 더미셀에 연결된 유사 비트라인인 노드 N31에 로우 데이타를 인가하는 트랜지시터 MN33과, 드레인이 하단 더미셀의 유사 비트라인인 노드 N32에 접속되고 게이트가 프리챠지 동작시 로직로우 상태를 일정시간 유지하는 S2 신호에 의해 제어되어 하단 더미셀에 연결된 유사 비트라인인 노드 N32에 하이 데이타를 인가하는 트랜지스터 MP33으로 이루어져, 상기의 유사 비트라인인 노드 N31과 노드 N32에 실제 셀의 데이타가 비트라인에 전달되었을 때와 같이, 프리챠지 동작시 1/2(Vcc)로 프리챠지 되어 있던 비트라인의 전위를 센싱마진 △V 정도 변화시켜 노드 N31에는 1/2(Vcc)-△V, 노드 N32에는 1/2(Vcc)+△V를 인가하는 회로 C와, 소오스는 RTO에 접속되고 게이트는 노드 N31에 연결된 트랜지스터 MP34와, 드레인은 상기의 MP34의 드레인에 접속되고 게이트는 프리챠지 동작시 로직하이 상태를 갖는 S3 신호에 의해 제어되며, 소오스는 그라운드 전위에 연결된 트랜지스터 MN32로 이루어진 RTO의 프리챠지 전위 Vcc와 1/2(Vcc) 사이로 유지시키는 회로 D와, 소오스는 /S에 접속되고 게이트는 노드 N32에 연결된 트랜지스터 MN34와, 드레인은 상기의 MN34의 드레인에 접속되고 게이트는 프리챠지 동작시 로직로우 상태를 갖는 S4 신호에 의해 제어되며, 소옷는 Vcc 전위에 연결된 트랜지스터 MP32로 이루어져 /S의 프리챠지 전위를 그라운드 Vss와 1/2(Vcc) 사이로 유지시키는 회로 E와, 상기 RTO, /S 사이에 다이오드 구조로 접속된 MP35, MN35와, 드레인 상기의 MN35의 소오스에 접속되고 드레인은 /S에 접속되며, 게이트는 프리챠지 동작시에 로직하이 상태를 가져 상기의 트랜지스터 MP35, MN35와 /S를 연결시키는 S5 신호에 의해 제어되는 MN36으로 이루어져, 상기의 RTO, /S 신호의 프리챠지 전위차가 Vtp + Vtn가 되도록 하는 회로F로 구성되어 있는 것을 특징으로 하는 비트라인 감지증폭기 제어신호 프리챠지 회로.In the bit line sense amplifier control signal precharge circuit of a DRAM device, the precharge potential of the bit line sense amplifier control signals RTO and / S is maintained at a potential between 1/2 (Vcc) and Vcc, and / S is a potential between 1/2 (Vcc) and Vss to reduce data access time and power consumption, so that the dummy cell A, the pseudo bit line B, the dummy word line for controlling the dummy cell, and the pseudo cell The precharge circuit G for precharging the bit line B, and the drain connected to the node N31 which is a similar bit line of the upper dummy cell and the gate controlled by the S1 signal maintaining the logic high state for a predetermined time during the precharge operation, Transistor MN33, which applies low data to node N31, a pseudo bit line connected to the dummy cell, and a drain is connected to node N32, which is a pseudo bit line of the lower dummy cell, and the gate is connected to logic during the precharge operation. The transistor MP33 applies high data to the node N32, which is a pseudo bit line connected to the lower dummy cell and controlled by the S2 signal which maintains the state for a certain time. As in the case of the transfer to the bit line, the potential of the bit line precharged to 1/2 (Vcc) during the precharge operation is changed by the sensing margin ΔV by about 1/2 (Vcc) -ΔV, A circuit C applying 1/2 (Vcc) + DELTA V to the node N32, a source connected to the RTO, a gate connected to the node N31, a drain connected to the drain of the MP34, and a gate precharged. Circuit D, which is controlled by the S3 signal having a high logic high state, and the source is maintained between the precharge potential Vcc and 1/2 (Vcc) of the RTO composed of the transistor MN32 connected to the ground potential, and the source is / S. A transistor MN34 connected with a gate connected to a node N32, a drain connected with a drain of the MN34, and a gate controlled by an S4 signal having a logic low state during a precharge operation, and the source consists of a transistor MP32 connected to a Vcc potential. A circuit E for maintaining the precharge potential of / S between ground Vss and 1/2 (Vcc), MP35 and MN35 connected in a diode structure between the RTO and / S, and the drain connected to the source of MN35. Is connected to / S, and the gate is made of MN36 which has a logic high state during the precharge operation and is controlled by the S5 signal connecting the transistors MP35 and MN35 and / S, and the RTO and / S signals are free. A bit line sense amplifier control signal precharge circuit, comprising a circuit F such that the charge potential difference becomes Vtp + Vtn. 제1항에 있어서, 비트라인 감지증폭기 제어신호 RTO의 프리챠지 전위는 1/2(Vcc)-△V(비트라인감지증폭기의 센싱마진)+Vtp(비트라인 감지증폭기의 NMOS 트랜지스터의 문턱전압), /S의 프리챠지 전위는 1/2(Vcc)+△V-Vtn(비트라인 감지증폭기의 PMOS 트랜지스터의 문턱전압)로 유지시키는 것을 특징으로 하는 비트라인 감지증폭기 제어신호 프리챠지 회로.The precharge potential of the bit line sense amplifier control signal RTO is 1/2 (Vcc) -ΔV (sense margin of the bit line sense amplifier) + Vtp (threshold voltage of the NMOS transistor of the bit line sense amplifier). And / S precharge potential is maintained at 1/2 (Vcc) +? V-Vtn (threshold voltage of PMOS transistor of bitline sense amplifier). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930009631A 1993-05-31 1993-05-31 Control signal precharge circuit for bit line sense amplifier KR100265602B1 (en)

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KR940026947A true KR940026947A (en) 1994-12-10
KR100265602B1 KR100265602B1 (en) 2000-09-15

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KR101154002B1 (en) * 2009-11-30 2012-06-08 에스케이하이닉스 주식회사 Voltage difference control circuit and semiconductor memory device

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