KR940020580A

KR940020580A - Bi-CMOS semiconductor device and manufacturing method

Info

Publication number: KR940020580A
Application number: KR1019930001349A
Authority: KR
Inventors: 김규철
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1993-02-01
Filing date: 1993-02-01
Publication date: 1994-09-16
Also published as: KR960008862B1

Abstract

본 발명은 주변회로 영역과 메모리 셀 영역으로 이루어진 반도체 Bi CMOS 구조에 있어서, 입력회로부의 V_IL(input low voltage)에 역 바이어스가 인가되는 경우 발생하는 데이터의 교란문제를 제거하기 위하여 기판과 반대의 도전형을 갖는 격리영역을 형성시켜 종래 -5V였던 네가키브 V_IL한계전압을 -0.5V로 크게 향상시킴으로써, 메모리 셀에 기억되어 있는 데이터가 없어지거나 뒤바뀌는 문제를 제거한 것이다.The present invention relates to a semiconductor Bi CMOS structure comprising a peripheral circuit region and a memory cell region of the substrate in the opposite order to remove the disturbance problem in the data that occur when applying a reverse bias to the V _IL (input low voltage) of the input circuit The isolation region having the conductivity type is formed to greatly increase the negative V _IL threshold voltage, which was -5V, to -0.5V, thereby eliminating or replacing data stored in the memory cell.

Description

Bi-CMOS semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 Bi-CMOS 반도체 장치의 구조를 개략적으로 설명하기 도면,1 is a diagram schematically illustrating a structure of a Bi-CMOS semiconductor device according to the present invention;

제2(A)도 내지 제2(I)도는 본 발명의 일실시예인 Bi-CMOS 반도체 장치의 제조방법을 나타내기 위한 공정단면도,2 (A) to 2 (I) are cross-sectional views illustrating a method of manufacturing a Bi-CMOS semiconductor device according to one embodiment of the present invention;

제3도는 종래 Bi-CMOS 장치의 저전압 입력단에 역 바이어스가 인가된 경우 나타나는 문제점을 설명하기 위한 개략도이다.3 is a schematic diagram illustrating a problem that occurs when a reverse bias is applied to a low voltage input terminal of a conventional Bi-CMOS device.

Claims

In a semiconductor Bi-CMOS structure, a first conductive substrate is divided into a peripheral circuit portion and a memory cell region by an element isolation region, and the first conductive lower layer has a low concentration buried layer of a second conductive type. A second region consisting of a region, a first region having a high conductivity type buried layer on said first region, a third region comprising a first conductive type low concentration well layer on said second region, and a left side of said first region BiCMOS semiconductor, characterized in that a structure in which the high concentration buried layer and the low concentration well layer of the second conductive type are in contact with each other in the peripheral circuit region and the memory cell region is formed on the upper right side and the left and right sides of the second and third regions, respectively. Device.

In the method of manufacturing a semiconductor Bi-CMOS, the first insulating film is formed on the substrate of the first conductive type, and then the portion to be the second conductive low concentration buried layer is defined by a photolithography process, and the heat treatment after the addition of the second conductive type impurity. To form a first region, form a second insulating film on the front surface of the substrate, and then form a second region, which is a high concentration buried layer of the first conductivity type, and form second conductive type high density investment layers on the left and right sides of the second region. Forming an epitaxial layer on the entire surface of the substrate, and then forming a third region, which is a low concentration well layer of a first conductivity type, and forming second conductive low concentration well layers on the left and right sides of the third region.

※ Note: The disclosure is based on the initial application.