KR940018856A - Recording data simultaneous recording circuit - Google Patents
Recording data simultaneous recording circuit Download PDFInfo
- Publication number
- KR940018856A KR940018856A KR1019930000245A KR930000245A KR940018856A KR 940018856 A KR940018856 A KR 940018856A KR 1019930000245 A KR1019930000245 A KR 1019930000245A KR 930000245 A KR930000245 A KR 930000245A KR 940018856 A KR940018856 A KR 940018856A
- Authority
- KR
- South Korea
- Prior art keywords
- osd
- recording
- video
- mixer
- recorded
- Prior art date
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- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
이 발명은 녹화시의 날짜와 시간을 동시에 녹화하기 위한 것으로서, 더욱 상세하게는 동시 녹화할 문자를 제공받아 비데오 신호와 믹서하는 제1OSD믹서부(30) 를 비데오 프로세서(40)의 입력단에 연결하고, 상기 비데오 프로세서(40)의 출력단에 비녹화 문자 데이타를 상기 비데오 프로세서(40)에서 출력되는 신호와 믹서하여 화면에 출력하는 제2 OSD믹서부(50)를 연결하여, 각 프로그램마다 녹화 초기에 일정시간동안 녹화시의 날짜와 시간이 동시에 녹화되도록 함으로써 각 프로그램이 언제 녹화되었는지 쉽게 구별할 수 있도록 하여 유저에게 편리함을 줄수 있다.The present invention is to record the date and time at the same time when recording, and more specifically, to connect the first OSD mixer unit 30, which is provided with a character to be recorded at the same time and the video signal to the input terminal of the video processor 40, And a second OSD mixer 50 for mixing the non-recorded text data with the signal output from the video processor 40 and outputting it to the screen at the output terminal of the video processor 40, so that each program is initially recorded. By recording the date and time when recording for a certain time at the same time, it is convenient for the user to easily distinguish when each program was recorded.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 이 발명에 따른 녹화 데이타 동시 녹화회로의 일실시예를 나타낸 블럭도, 제2도는 이 발명에 따른 녹화 데이타 동시 녹화를 수행하기 위한 흐름도이다.1 is a block diagram showing an embodiment of a recording data simultaneous recording circuit according to the present invention, and FIG. 2 is a flowchart for performing simultaneous recording of recording data according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930000245A KR940018856A (en) | 1993-01-11 | 1993-01-11 | Recording data simultaneous recording circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930000245A KR940018856A (en) | 1993-01-11 | 1993-01-11 | Recording data simultaneous recording circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940018856A true KR940018856A (en) | 1994-08-19 |
Family
ID=66865932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930000245A KR940018856A (en) | 1993-01-11 | 1993-01-11 | Recording data simultaneous recording circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940018856A (en) |
-
1993
- 1993-01-11 KR KR1019930000245A patent/KR940018856A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |