KR940016153A - Peak-value detection circuit of V-seal PG and FG - Google Patents

Peak-value detection circuit of V-seal PG and FG Download PDF

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Publication number
KR940016153A
KR940016153A KR1019920026801A KR920026801A KR940016153A KR 940016153 A KR940016153 A KR 940016153A KR 1019920026801 A KR1019920026801 A KR 1019920026801A KR 920026801 A KR920026801 A KR 920026801A KR 940016153 A KR940016153 A KR 940016153A
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KR
South Korea
Prior art keywords
analog
clock
digital converter
register
signals
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Application number
KR1019920026801A
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Korean (ko)
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KR100257511B1 (en
Inventor
백복현
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이헌조
주식회사 금성사
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Priority to KR1019920026801A priority Critical patent/KR100257511B1/en
Publication of KR940016153A publication Critical patent/KR940016153A/en
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Publication of KR100257511B1 publication Critical patent/KR100257511B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/24—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by sensing features on the record carrier other than the transducing track ; sensing signals or marks recorded by another method than the main recording
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

본 발명은 브이씨알의 서보계의 PG,FG의 피크치를 검출하여 진폭병동에도 주기가 일정한 PG,FG 신호를 출력시키고자 한 브이씨알의 PG,FG의 피크치 검출회로에 관한 것으로서, 이러한 본 발명의 목적은 PG,FG 신호를 디지탈 신호로 변환하는 아날로그/디지탈 변환부(1)와, 클럭펄스를 발생하는 클럭발생부(2)와, 상기 아날로그/디지탈 변환부(1)에서 출력된 데이타를 상기 클럭발생부(2)에서 얻어진 클럭에 동기시켜 일시 저장하는 제1,제2레지스터(3)(4)와, 상기 아날로그/디지탈 변환부(1)에서 출력된 데이타를 1클럭 지연시켜 저장하는 제3레지스터(5)와, 상기 제3레지스터(5)에서 얻어진 데이타와 상기 제2레지스터(4)에서 얻어진 데이타를 감산하여 피크치를 검출하는 감산부(6)와, 상기 감산부(6)에서 출력된 신호에 따라 세트되어 전압을 시정수만큼 지연시켜 출력하는 멀티 바이브레이터(7)를 구비함으로써 달성된다.The present invention relates to a peak value detection circuit for PG and FG of VRL which detects peak values of PG and FG of a servo system and outputs PG and FG signals having a constant period even in an amplitude ward. The purpose is to convert the PG and FG signals into digital signals, the analog / digital converter 1, the clock generator 2 to generate a clock pulse, and the data output from the analog / digital converter 1 A first and second registers (3) and (4), which are temporarily stored in synchronization with the clock obtained by the clock generator (2), and the first and second data for delaying and storing the data output from the analog / digital converter (1). A subtractor (6) for subtracting the three registers (5), the data obtained from the third register (5) and the data obtained from the second register (4) to detect peak values, and outputting from the subtractor (6) It is set according to the set signal and delays the voltage by time constant. Which is achieved by having a multi-vibrator (7).

Description

브이씨알의 피지(PG), 에프지(FG)의 피크(Peak)치 검출회로Peak-value detection circuit of V-seal PG and FG

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제1도의 각 부 입출력 파형도, 제3도는 본 발명 브이씨알의 PG,FG의 피크치 검출회로도, 제4도는 제3도의 각 부 입출력 파형도.FIG. 2 is a diagram of each sub-input / input waveform of FIG. 1, FIG. 3 is a peak value detection circuit diagram of PG and FG of the VR of the present invention, and FIG.

Claims (1)

PG,FG 신호를 디지탈 신호로 변환하는 아날로그/디지탈 변환부(1)와, 클럭펄스를 발생하는 클럭발생부(2)와, 상기 아날로그/디지탈 변환부(1)에서 출력된 데이타를 상기 클럭 발생부(2)에서 얻어진 클럭에 동기시켜 일시 저장하는 제1,제2레지스터(3)(4)와, 상기 아날로그/디지탈 변환부(1)에서 출력된 데이타를 1클럭 지연시켜 저장하는 제3레지스터(5)와, 상기 제3레지스터(5)에서 얻어진 데이타와 상기 제2레지스터(4)에서 얻어진 데이타를 감산하여 피크치를 검출하는 감산부(6)와, 상기 감산부(6)에서 출력된 신호에 따라 세트되어 전압을 시정수만큼 지연시켜 출력하는 멀티 바이브레이터(7)를 포함하여 된 것을 특징으로 한브이씨알의 PG,FG의 피크치 검출회로.An analog / digital converter 1 for converting PG and FG signals into a digital signal, a clock generator 2 for generating a clock pulse, and data output from the analog / digital converter 1 are generated for the clock. The first and second registers 3 and 4, which are temporarily stored in synchronization with the clock obtained in the section 2, and the third register, which is delayed by one clock and stored in the data output from the analog / digital converter 1; (5), a subtractor 6 for detecting peak values by subtracting the data obtained from the third register 5 and the data obtained from the second register 4, and the signal output from the subtractor 6; And a multivibrator (7) which is set in accordance with the present invention and outputs the voltage by delaying the voltage by a time constant. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026801A 1992-12-30 1992-12-30 V-seal sebum, f-ji peak detection circuit KR100257511B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026801A KR100257511B1 (en) 1992-12-30 1992-12-30 V-seal sebum, f-ji peak detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026801A KR100257511B1 (en) 1992-12-30 1992-12-30 V-seal sebum, f-ji peak detection circuit

Publications (2)

Publication Number Publication Date
KR940016153A true KR940016153A (en) 1994-07-22
KR100257511B1 KR100257511B1 (en) 2000-06-01

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ID=19347936

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026801A KR100257511B1 (en) 1992-12-30 1992-12-30 V-seal sebum, f-ji peak detection circuit

Country Status (1)

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KR (1) KR100257511B1 (en)

Also Published As

Publication number Publication date
KR100257511B1 (en) 2000-06-01

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