KR940012936A - Time division multiplexer - Google Patents
Time division multiplexer Download PDFInfo
- Publication number
- KR940012936A KR940012936A KR1019920020828A KR920020828A KR940012936A KR 940012936 A KR940012936 A KR 940012936A KR 1019920020828 A KR1019920020828 A KR 1019920020828A KR 920020828 A KR920020828 A KR 920020828A KR 940012936 A KR940012936 A KR 940012936A
- Authority
- KR
- South Korea
- Prior art keywords
- count
- time division
- integer
- register
- crn
- Prior art date
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- Time-Division Multiplex Systems (AREA)
Abstract
본 발명은 프레임내의 각 타임 슬롯을 단위 대역폭의 정수배로 제어 가능하게 하여 임의의 대역폭으로 할당되도록 한 시분할 다중화 장치에 관한 것으로, 이러한 본 발명은 프레임내의 각 타임 슬롯에 원하는 카운트 정수값을 할당하기 위한 카운트 정수 레지스터(CR1-CRn)와, 카운트 정수 레지스터(CR1-CRn)에 의해 로드된 정수 값을 다운 카운트하는 다운카운터(DC1-DCn)를 송신단과 수신단의 양쪽에 구성된 바이트 동기 클럭 로직부와 쉬프트 레지스터에 각각 연결하여 송수신단에 동일하게 설정된 카운트 정수값에 따라 각 타임 슬롯을 변화시키게 된다.The present invention relates to a time division multiplexing apparatus in which each time slot in a frame is controllable by an integer multiple of the unit bandwidth so that it is allocated to an arbitrary bandwidth. The present invention is directed to assigning a desired count integer value to each time slot in a frame. A byte synchronization clock logic unit configured to both count and register the down-counter DC1-DCn for down counting the integer value loaded by the count-integer registers CR1-CRn and the count-integer registers CR1-CRn. Each time slot is changed according to the count integer value set in the transmitter and receiver by connecting to each register.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명 시분할 다중화 장치의 송신단 블록 구성도,3 is a block diagram of a transmitting end of a time division multiplexing apparatus of the present invention;
제4도는 본 발명의 시분할 다중화 방식에서의 프레임 구성도,4 is a frame diagram of a time division multiplexing scheme of the present invention;
제5도의 (가)-(다)는 제3도에서 카운트 정수가 2일 경우의 타임 슬롯(T/S1)에 대한 신호 타이밍도.5A to 5C are signal timing diagrams for the time slot T / S1 when the count integer is 2 in FIG.
제6도는 본 발명 시분할 다중화 장치의 수신단 블럭 구성도.6 is a block diagram of the receiving end of the time division multiplexing apparatus of the present invention.
제7도의 (가)-(다)는 제6도에서 카운트 정수가 2일 경우의 타임슬롯(T/S1)에 대한 신호 타이밍도.7A to 7C are signal timing diagrams for the timeslot T / S1 when the count constant is 2 in FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020828A KR940012936A (en) | 1992-11-06 | 1992-11-06 | Time division multiplexer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020828A KR940012936A (en) | 1992-11-06 | 1992-11-06 | Time division multiplexer |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940012936A true KR940012936A (en) | 1994-06-24 |
Family
ID=67210188
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920020828A KR940012936A (en) | 1992-11-06 | 1992-11-06 | Time division multiplexer |
Country Status (1)
Country | Link |
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KR (1) | KR940012936A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100373732B1 (en) * | 1997-07-09 | 2003-02-26 | 윈스타 코뮤니케이션즈, 인코포레이티드 | Computer controlled multi-service subscriber radio unit |
US8223726B2 (en) | 1997-06-19 | 2012-07-17 | Idt Capital, Inc. | Metropolitan wide area network |
-
1992
- 1992-11-06 KR KR1019920020828A patent/KR940012936A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8223726B2 (en) | 1997-06-19 | 2012-07-17 | Idt Capital, Inc. | Metropolitan wide area network |
KR100373732B1 (en) * | 1997-07-09 | 2003-02-26 | 윈스타 코뮤니케이션즈, 인코포레이티드 | Computer controlled multi-service subscriber radio unit |
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