KR940012357A - 8/11 digital modulation / demodulation encoder - Google Patents

Abstract

The present invention relates to a digital modulation / demodulation coder. The lookup table (LUT1) is composed of 11-bit NRZ-I code blocks having a CDS of -1 or _1 and a line-length of 0 or less, and a DSV. Depending on the polarity of the DSV detected by the detector 40 and the polarity detector 50 and the LNB of the previous MRZ-I code block, the MSB inverter 60 and the MSB inverter 70 are 11-bit NRZ-I code blocks. By appropriately converting the MSB, the 8-bit data block can be modulated with an 11-bit NRZ-I code block. In addition, the present invention provides a lookup table of a demodulator with 8-bit data blocks corresponding to the remaining 10 bits of the 11-bit NRZ-I code blocks of which CDS is ± 1 and 0 has a line-length of 3 or less. The 11-bit NRZ-I code block is easily demodulated into a 10-bit data block.

Description

8/11 digital modulation / demodulation encoder

As this is a public information case, the full text was not included.

1 is a block diagram showing an input / output relationship of a lookup table used in the 8/11 digital modulation / demodulation coding apparatus of the present invention;

2 is a block diagram of an 8/11 digital modulation coding apparatus according to the present invention;

3 is a block diagram showing another embodiment of the 8/11 digital modulation and coding apparatus according to the present invention.

Claims (15)

A digital modulation code apparatus, comprising: storage means for converting 8-bit input data blocks into 11-bit NRZ-I code blocks having a CDS of -1 and a line-length of 0 or less; DSV detecting means for detecting the polarity of the DSV of the applied 11-bit NRZ-I code blocks; Polarity detecting means for detecting LSB polarity of an applied 11-bit NRZ-I code block; MSB inverting discrimination means for outputting a logic signal indicating whether the MSB is inverted according to the DSV polarity of the DSV detecting means and the LBS polarity detected by the polarity detecting means; MSB inverting means for receiving an MSB of the 11-bit NRZ-I codes of the storage means and selectively inverting and applying the MSB according to a logic signal of the MSB inverting discrimination means; The output bit code of the MSB inverting means is combined with the MSB in the lower 10 bits of the 11-bit NRZ-I code blocks of the storage means and output as an 11-bit NRZ-I code block corresponding to 8-bit data, and the DSV detection is performed. An 8/11 digital modulation / coding device comprising means for synthesizing means and means for applying polarity detecting means. 2. The apparatus of claim 1, wherein the storage means comprises: a first lookup table for converting 8-bit input data blocks into 11-bit NRZ-I code blocks having a CDS of -1 and a line-length of 0 or less; ; And an eighth latching means for latching an output of said first lookup table for a predetermined time. The 8/11 digital modulation / coding device according to claim 1, wherein the MSB inverting discrimination means comprises a first exclusive oragate. The 8/11 digital modulation and coding device according to claim 1, wherein the MSB inverting means comprises a second exclusive orifice. 2. The synthesizing means according to claim 1, wherein the synthesizing means inputs the lower 10 bits of the 11-bit NRZ-I code blocks and the 1-bit code of the MSV inverting means in parallel from the storage means, and 1 of the MSB inverting means. 8. An 8/11 digital modulation coder having a first parallel serial shifter register that is serially output in series with the 10-bit NRZ0I code block using a bit code as the MSB. 2. The storage means according to claim 1, wherein the storage means stores 8-bit input data blocks of NRZ- of a predetermined higher bit among 11-bit NRZ-I code blocks having a CDS of -1 and a line-length of 0 or less. A second lookup table for converting into I code blocks and outputting the second lookup table; The NRZ- of the remaining lower bits of the 11-bit NRZ-I code blocks of 8-bit input data blocks whose CDS is -1 and whose line-length of 0 is 3 or less are not converted by the second lookup table. A third lookup table for converting into I code blocks and outputting the same; And an eighth latch means for latching an NRZ-I code block of the third lookup table for a predetermined time. The MSB inverting means according to claim 1, wherein the synthesizing means inputs in parallel the predetermined high bit codes excluding the MSB of the 11-bit NRZ-I code blocks of the storage means and the output 1-bit code of the MSB inverting means. A second parallel serial shift register for sequentially outputting the NRZ-I codes inputted with the 1-bit code of MSB as MSB; A third parallel serial shift register for sequentially inputting only a predetermined lower bit code block of the 11 bit NRZ-I code blocks of the storage means in parallel and sequentially outputting the same; 8/7 for outputting the output of the second and third parallel shift shift registers, and outputting the code blocks of the second parallel shift shift register as upper bits and the code blocks of the third parallel shift shift register as lower bits. 11 Digital Modulation Coder. 1. A digital modulation coder, comprising: storage means for converting 8-bit input data blocks into 11-bit NRZ-I code blocks having a CDS of +1 and a line-length of 0 or less; DSV detecting means for detecting the polarity of the DSV of the applied 11-bit NRZ-I code blocks; Polarity detecting means for detecting an LNB polarity of an applied 11-bit NRZ-I code block; MSB inversion discrimination means for outputting a logic signal informing whether the MSB is inverted according to the DSV polarity of the DSV detecting means and the LNB polarity detected by the polarity detecting means; MSB inverting means for receiving an MSB of the 11-bit NRZ-I codes of the storage means and selectively inverting and applying the MSB according to a logic signal of the MSB inverting discrimination means; The output bit code of the MSB inverting means of the lower 10 bits of the 11-bit NRZ-I code blocks of the storage means is synthesized into an MSB and output as an 11-bit NRZ-I code block corresponding to 8-bit data. An 8/11 digital modulation coding apparatus comprising a combining means applied to a detecting means and a polarity detecting means. 9. The apparatus of claim 8, wherein the storage means comprises: a fourth lookup table for converting 8-bit input data blocks into 11-bit NRZ-I code blocks having a CDS of +1 and a length of 0 or less; ; And an first latch means for latching an output of said first lookup table for a predetermined time. 9. The 8/11 digital modulation and coding device according to claim 8, wherein the MSB inverting means comprises a third exclusive or gate and an inverter connected to the exclusive or gate. The 8/11 digital modulation and coding device according to claim 8, wherein the MSB inverting means comprises a fourth exclusive orifice. 10. The MSB inverting means of claim 8, wherein the synthesizing means inputs a lower 10-bit code of the 11-bit NRZ-I code blocks and the 1-bit code of the MSB inverting means in parallel from the storage means, And a fourth parallel serial indicator register sequentially outputting in series with the 10-bit NRZ-I code block using a bit code as an MSB. The data storage device of claim 8, wherein the storage means stores 8-bit input data blocks of NRZ- of a predetermined higher bit among 11-bit NRZ-I code blocks having a CDS of +1 and a line-length of 0 or less. A fifth lookup table which is converted into I code blocks and outputted; NRZ- of the remaining lower bits of the 11-bit NRZ-I code blocks of 8-bit input data blocks whose CDS is +1 and whose line-length is 0 or less are not converted by the fifth lookup table. A sixth lookup table for converting into I code blocks and outputting the same; And an eighth latch means for latching an NRZ-I code block of the sixth lookup table for a predetermined time. 10. The MSB inverter according to claim 8, wherein the combining means inputs in parallel the predetermined high bit codes excluding the MSB of the 11-bit NRZ-I code blocks of the storage means and the output 1-bit code of the MSB inverting means. A fifth parallel serial shift register for serially outputting the NRZ-I codes inputted with the 1-bit code of MSB as the MSB; A sixth parallel shift shift register for serially inputting only a predetermined lower bit code block among the 11 bit NRZ-I code blocks of the storage means in parallel and sequentially outputting it; 8/7 for outputting the output of the fifth and sixth parallel shifter registers, and outputting the code block of the fifth parallel shifter register as the upper bit and the code block of the sixth parallel shifter register as the lower bit. 11 Digital Modulation Coder. A device for decoding blocks modulated with an 11-bit NRZ-I code whose CDS is ± 1 and a line-length of 0 or less is 3 into an 8-bit data block. The 11-bit NRZ-I code blocks are serially inputted. A parallel and parallel shift register for outputting NRZ-I code blocks of the lower 10 bits except MSB in parallel; 11 bits of NRZ-I code blocks having a CDS of ± 1 and a line-length of 0 or less have 8 bits of data blocks corresponding to the remaining 10 bits except for the MSB, and are applied from the serial-to-parallel shifter register. A lookup table for outputting an 8-bit data block corresponding to a 10-bit NRZ-I code block; And an eighth parallel serial shift register configured to sequentially input 8-bit data blocks of the lookup table in parallel and sequentially output the same. ※ Note: The disclosure is based on the initial application.