KR940010476B1 - Picture half tone processing device of fax - Google Patents

Abstract

The device comprises a binary counter (2) for counting a clock signal by 1728, a quarternion counter (4) for counting a carry signal of the binary counter (2), a converter (3) for converting digital signal to analog signal according to clock signal (c) by connecting output ports (Q0,Q1) of the binary counter and the counter (4) with input ports (I2,I1,I3,I0), and a comparator (1) for comparing D/A converter (3) with levels of an image signal (I) and outputting a half-tone signal.

Description

Image Pseudo Gradient Processing Unit

1 is a block diagram of a conventional pseudo gray scale processing apparatus.

2 is a circuit diagram of the device of the present invention.

3 is a diagram for explaining the operation of the device of the present invention.

4 is a diagram showing the contrast level of the device of the present invention.

5 is ROM internal data of a conventional apparatus.

6 is a diagram showing an analog reference contrast level of the device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pseudo gradation processing apparatus of a simulated transmitter, and more particularly, to an image pseudo gradation of a simulated transmitter capable of performing pseudo gradation using a counter and a digital analog converter without using ROM (Read Only Memory). It relates to a processing apparatus.

The simulation transmitter can transmit only the pixels of two states, which are shown in black and white, when the image is transmitted to the counterpart simulation transmitter.

Therefore, an image having multiple levels of contrast level LEVEL, such as a photograph, has a disadvantage in that it is not transmitted efficiently. One solution to this drawback is that the GPOUPIII simulated transmitter, which can be easily bonded in general, has a HALF-TONE processing function.

This pseudo-gradation processing function is a function of processing a pixel in a state where a certain level of contrast can be felt when a human eye sees an image having fine contrast, such as a photograph, only with two states of black or white pixels.

When the image processing is performed in the GROUPIIIFAX device in the standard mode, the pixel size is 1/8 mm wide and 1 / 3.85 m long. In FIG. 3, only 4 pixels are displayed horizontally and 4 pixels vertically. In fact, when the image is A4 size (SIZE), since there are 1728 pixels (216 x 8 dots / mm) in the horizontal direction, the matrix MATRIX shown in FIG. 3 is repeatedly displayed 512 times.

Therefore, the matrix shown in FIG. 3 can be regarded as one large pixel that can display 16 light and dark levels by collecting 16 adjacent small pixels.

According to the number of black pixels among the 16 small pixels in such a matrix, the contrast level of the matrix can be represented in 16 steps from "0" to "15" as in the fourth degree. The meaning of the number given to the small pixels existing in the matrix indicates the level of contrast of black and white determination of the small pixels.

Therefore, the pixel 1 is determined to be black or white on the basis of step 1 of the standard contrast 16 steps, and the criteria of pixel 2 are determined to be black or white on the basis of step 2 in the same manner.

For example, in an image having a contrast level of 10.5, only pixels 11, 12, 13, 14, 15, and 15 in the matrix are black, and all the remaining pixels are white.

In Fig. 1, a conventional technical configuration for performing the sixteen sets of pseudo gradation processing described above is shown in a block diagram.

Reference contrast data (0-15) are stored in the ROM. According to the matrix structure shown in FIG. 3, the data stored in the ROM is the same as the fifth figure.

The data from address (0) to 1727 is for the first line processing in the image of A4 size (each line is composed of 1728 pixels), and the second line, the third line, the fourth line processing in the same way. Represents data for.

The fifth line is iteratively processed again with the first line data.

The counter for counting the clock inputs the counted value according to the number of clocks inputted into the ROM address, and the ROM outputs reference contrast data stored at the address and inputs it to the digital / analog converter. At this time, the analog value corresponding to the reference contrast data generated by the digital / analog converter becomes the black and white determination reference value of the comparator, and the analog pixels of one line are sequentially outputted one pixel at a time in synchronization with the clock from the image input sensor. Pseudo-gradation processing.

The counter consists of a 6912 (1728 x 4) binary counter, which is reset to " 0 " at the beginning of the image processing to process the first pixel of the first line.

Therefore, " 1 " stored at an address corresponding to the counter value of the counter is analogized to the value of the reference contrast level " 1 " in FIG. 6 through the digital / analog converter and input to the comparator. In this way, the first pixel successively output from the image input sensor is pseudo gray scale processing, and the remaining pixels of the following pixels are pseudo gray scale processing in the same manner.

For example, in the A4 size copy transmitter, 1728 analog pixels (2048 if the paper is B4) are continuously applied to the comparator of the pseudo gradation processing device in synchronization with a clock. Pseudo-gradation processing is performed digitally, but the conventional apparatus configured as the first diagram requires ROM (8 × 8 kilobyte capacity when the paper is A4 size), which increases the volume of the simulation transmitter and increases the product cost. There is this.

In order to solve the above disadvantages, the present invention connects a counter directly to a digital / analog converter to enable pseudo-gradation processing of an image signal without a ROM, thereby minimizing the volume of the simulation transmitter and reducing the manufacturing cost. An object of the present invention will be described in detail with reference to the accompanying drawings.

2, the apparatus of the present invention connects the video signal input I to one input of the comparator 1, and connects the clock signal C input to the 1728 binary binary counter 2 and the digital / analog converter 3. Is connected to the clock input CK and outputs the QQ and Q1 of the 1728 binary binary counter 2 and the quaternary binary counter 4 that counts the carry of the 1728 binary binary counter. (Q0, Q1) is connected to the inputs (I2, I1, I3, I0) of the digital / analog converter 3, and the output of the digital / analog converter 3 is connected to the other input of the comparator 1 to be.

&Quot; I " represents pixels that are continuously output in synchronization with the clock C in the image input sensor. After resetting the counters 2 and 4, the image input sensor inputs the image of the first line. At this time, in the counter 2, the count value "0" is input to the digital-to-analog converter 3 to become the black and white determination reference value of the first pixel of the image input sensor. When the clock C is input once for processing the second pixel, the second pixel is output from the image input sensor and the count value of the counter 2 is in the state of "1".

The " 1 " state of the counter 2 is input to the digital / analog converter 3 in a state of " 4 " and becomes a black and white determination reference value of the second pixel of the first line as shown in FIG. After all of the first line consisting of the 1728 counter is in the "0" state and the carry over the binary binary counter (4) is the state of "1". At this time, the " 8 " state is input to the digital / analog converter 3 to process the first pixel of the second line output from the image input sensor. In the same manner, the pixels of the third line and the fourth line are sequentially processed, and the operation of the signal consisting of 1728 pixels in one line is described in detail. For example, the output terminal Q0 of the 1728 binary binary counter 2 is described in detail. Q1) and 1728 Binary Binary Counters The signals of the output terminals Q0 and Q1 of the Binary Binary Counters 4, which count the carry signals of the 1728 Binary Binary Counters 2, are inputted by the digital / analog converter 3; Since it is used as a signal of the terminals I2, I1, I3, I0, the digital-to-analog converter 3 has 0, 4, 2, 6 of the input terminals I0-I3 until the clock C is input. Four digital values are repeatedly input to the reference value of the first line to the comparator 1, and the digital values of 8, 12, 10, and 14 are repeatedly input to the reference value of the second line in the clock 1728-3455 period, and the clock is The third line with a repeat input of 1,5,3,7 in the period of 3456-5183, the fourth with a repeat input of 9,13,11,15 in the period of clock 5184-6911 It is a reference value ins and the pseudo-gray-scale processing.

According to the present invention as described above can be performed pseudo-gradation processing analog video signal without ROM simple and cheaper than the conventional technical configuration, the volume of the replica transmitter can be reduced, and the manufacturing cost can be reduced.

Claims (1)

A 1728 binary binary counter 2 that counts a clock signal C 1728, a quaternary binary counter 4 that quaternizes a carry signal of the 1728 binary binary counter 2, and the 1728 binary bypass. The signal of the output terminals Q10 and Q11 of the branch counter 2 is the signal of the input terminals I2 and I1, and the signal of the output terminals Q10 and Q11 of the binary binary counter 4 is the input terminal ( By comparing the levels of the digital / analog converter 3 and the digital / analog converter 3 and the image signal I, which are converted into an analog signal according to the clock signal C as the signals of I3 and I0, the pseudo gradation is compared. An image pseudo gradation processing apparatus of a simulation transmitter, characterized by comprising a comparator (1) outputting a processing signal.

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