KR940008907B1 - Dc-dc converter - Google Patents
Dc-dc converter Download PDFInfo
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- KR940008907B1 KR940008907B1 KR1019920011497A KR920011497A KR940008907B1 KR 940008907 B1 KR940008907 B1 KR 940008907B1 KR 1019920011497 A KR1019920011497 A KR 1019920011497A KR 920011497 A KR920011497 A KR 920011497A KR 940008907 B1 KR940008907 B1 KR 940008907B1
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- fet
- pwm
- transformer
- voltage
- converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
제1도는 종래의 DC-DC 콘버터 회로도.1 is a circuit diagram of a conventional DC-DC converter.
제2도는 이 발명에 따른 DC-DC 콘버터 회로도.2 is a circuit diagram of a DC-DC converter according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : PWM IC 20 : 버퍼10: PWM IC 20: Buffer
Q1,Q2,Q3 : FET D1,D2 : 다이오드Q1, Q2, Q3: FET D1, D2: Diode
D3,D4 : 기생다이오드 L1 : 초크코일D3, D4: Parasitic Diode L1: Choke Coil
C1 : 콘데서 T1 : 트랜스C1: Condenser T1: Trance
이 발명은 전원장치에 관한 것으로서, 보다 상세하게는 콘버터의 회로를 개선하여 고효율을 얻을 수 있도록 한 DC-DC 콘버터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device, and more particularly, to a DC-DC converter capable of obtaining high efficiency by improving a circuit of a converter.
종래의 DC-DC 콘버터은 제1도에서와 같이 트랜수(T1)의 1차측에 연결된 스위칭 소자인 FET(Q1)가 PWM IC(10)에 의해 온되면, 트랜스(T1)의 2차측으로 전압이 유기되어 2차측에서 다이오드(D1)와 콘덴서(C1)를 통해 전류(i1)가 흐르게 되어 전류루프를 형성하게 되고, 상기 FET(Q1)가 오프되면 코일(L1)에 축척된 에너지에 의해 전류(i2)가 다이오드(D2)를 통해 흐르게 되어 루프가 형성된다.In the conventional DC-DC converter, as shown in FIG. 1, when the FET Q1, which is a switching element connected to the primary side of the transistor T1, is turned on by the PWM IC 10, the voltage is transferred to the secondary side of the transformer T1. When the FET Q1 is turned off, the current i1 flows through the diode D1 and the capacitor C1 at the secondary side to form a current loop. When the FET Q1 is turned off, the current is accumulated by the energy accumulated in the coil L1. i2) flows through diode D2 to form a loop.
제1도와 같은 종래의 기술은 상기 다이오드(D1),(D2)의 드롭전압이 높아 열이 많이 발생하게 되어 효율이 70∼80%로 저화되는 원인이 되었다.The prior art as shown in FIG. 1 causes high drop voltages of the diodes D1 and D2 to generate a lot of heat, thereby lowering the efficiency to 70 to 80%.
이와같은 문제를 해결하기 위해서는 상기 트랜스의 2차측의 회로구성을 개선하여 효율저하를 방지할 수 있다.In order to solve such a problem, it is possible to improve the circuit configuration of the secondary side of the transformer to prevent the efficiency decrease.
이 발명은 이와 같은 문제점을 해결하기 위한 것으로서, 이 발명의 목적은 상기 트랜스 2차측의 회로에서 다이오드를 이용한 회로를 온시에 매우 낮은 드레인 소스간의 내부저항을 가지는 MOSFET를 이용한 회로로 개선시키고 MOSFET를 버퍼를 이용한 드라이브를 행하도록 되어 고효율을 얻을 수 있게 된 DC-DC 콘버터를 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to improve the circuit using a diode in the circuit of the transformer secondary side to a circuit using a MOSFET having an internal resistance between drain sources at a very low level and to buffer the MOSFET. It is to provide a DC-DC converter that can be obtained by performing a drive using a high efficiency.
이와 같은 목적을 달성하기 위한 이 발명은, PWM IC와 이 PWM IC에 의해 스위칭되는 스위칭소자와 이 스위칭소자의 스위칭에 의해 2차측으로 전압을 유기되는 트랜스와 이 트랜스의 2차측에 연결되어 유기된 전압을 직류로 변환시켜 출력하는 정류평활회로를 구비한 콘버터회로에 있어서, 상기 트랜스의 2차측에 연결된 정류평활회로는, 2차측의 권선일측에 연결된 FET와, 이 FET의 일측과 2차측 권선의 다른 일측간에 설치된 FET와, 이 FET로부터 출력되는 전압을 평활시키는 초크코일 및 콘덴서로 이루어지고, 상기 2단의 FET는 각기 버퍼의 출력에 게이트가 연결되고, 이 버퍼는 상기 PWM IC의 출력에 연결된 것을 특징으로 하는 DC-DC 콘버터에 그 특징이 있다.In order to achieve the above object, the present invention relates to a PWM IC, a switching device switched by the PWM IC, a transformer inducing voltage to the secondary side by switching of the switching device, and connected to the secondary side of the transformer. In a converter circuit having a rectifying smoothing circuit for converting and outputting a voltage into a direct current, the rectifying smoothing circuit connected to the secondary side of the transformer includes a FET connected to one side of the secondary side winding, and one side of the FET and a secondary side winding. FETs installed between the other sides and choke coils and capacitors for smoothing the voltage output from the FETs. The two-stage FETs have their gates connected to the outputs of the buffers, which are connected to the outputs of the PWM ICs. It is characterized by the DC-DC converter characterized in that.
이하, 이 발명에 따른 DC-DC 콘버터의 실시예에 대하여 첨부도면에 따라서 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of a DC-DC converter according to the present invention will be described in detail with reference to the accompanying drawings.
제2도는 이 발명에 따른 DC-DC 콘버터의 회로도를 나타낸 것으로서, PWM IC(10)와 이 PWM IC(10)에 의해 스위칭되는 스위칭소자인 FET(Q1)와 이 스위칭소자의 스위칭에 의해 2차측으로 전압이 유기되는 트랜스(T1)와 이 트랜스(T1)의 2차측에 연결되어 유기된 전압을 직류로 변환시켜 출력하는 정류평활회로를 구비한 콘버터회로에 있어서, 상기 트랜스(T1)의 2차측에 연결된 정류평활회로는, 2차측의 권선일측에 연결된 FET(Q2)와, 이 FET(Q2)의 일측과 2차측 권선의 다른 일측간에 설치된 FET(Q3)와, 이 FET(Q3)로부터 출력되는 전압을 평활시키는 초크코일(L1) 및 콘덴서(C1)로 이루어지고, 상기 2단의 FET(Q2),(Q3)는 각기 버퍼(20)의 출력에 게이트가 연결되고, 이 버퍼(20)는 상기 PWM IC(10)의 출력에 연결되어 PWM IC(10)의 출력에 의해 상기 FET(Q2),(Q3)를 구동시키도록 되었다.2 shows a circuit diagram of the DC-DC converter according to the present invention, in which the secondary side is switched by switching the PWM IC 10 and the FET Q1 which is a switching element switched by the PWM IC 10 and the switching element. A converter circuit having a rectifier smoothing circuit having a transformer T1 for which voltage is induced and a rectified smoothing circuit connected to the secondary side of the transformer T1 and converting the induced voltage into a direct current, the secondary side of the transformer T1 The rectification smoothing circuit connected to the FET Q2 connected to one side of the secondary winding, the FET Q3 provided between one side of the FET Q2 and the other side of the secondary winding, and the output from the FET Q3 It is composed of choke coil L1 and capacitor C1 to smooth the voltage. The two-stage FETs Q2 and Q3 are gated to the output of the buffer 20, respectively. It is connected to the output of the PWM IC 10 to drive the FETs Q2 and Q3 by the output of the PWM IC 10.
이와 같이 구성된 이 발명은 상기 FET(Q2),(Q3)는 온시에 드레인 소스간의 내부저항이 매우 낮은 MOSFET로 설정하였다. 제2도에서 FET(Q2),(Q3)의 드레인 소스간에 설치되어 있는 다이오드(D3),(D4)는 FET(Q2),(Q3)의 내부에 기생하는 기생다이오드를 나타낸 것이다.According to the present invention configured as described above, the FETs Q2 and Q3 are set to MOSFETs having a very low internal resistance between drain sources when turned on. In FIG. 2, the diodes D3 and D4 provided between the drain sources of the FETs Q2 and Q3 represent parasitic diodes parasitic inside the FETs Q2 and Q3.
이와 같이 구성된 이 발명은, 트랜스(T1) 1차측에 연결된 FET(Q)가 PWM IC(10)에 의해 온되면 트랜스(T1)의 2차측에서는 FET(Q2)를 통해 폐루프가 형성되며, 상기 FET(Q1)가 오프되면 초크코일(L1)에 축척된 에너지는 FET(Q3)의 기생다이오드(D4)를 통해 흐르게 되어 폐루프가 형성된다. 이때 상기 FET(Q2)(Q3)의 드레인과 소스간의 내부 저항이 매우 적으므로 드롭전압이 낮게 되고, 이에 따라서 소자의 열발생이 적게 된다.According to the present invention configured as described above, when the FET Q connected to the primary of the transformer T1 is turned on by the PWM IC 10, a closed loop is formed through the FET Q2 at the secondary side of the transformer T1. When the FET Q1 is turned off, the energy accumulated in the choke coil L1 flows through the parasitic diode D4 of the FET Q3 to form a closed loop. At this time, since the internal resistance between the drain and the source of the FETs Q2 and Q3 is very small, the drop voltage is low, thereby reducing the heat generation of the device.
또한 FET(Q2)(Q3)는 PWM IC(10)의 출력을 버퍼(20)을 통해 구동신호로 제공받게 되므로 트랜스(T1)의 2차측의 회로가 1차측과 동기되어 구동되며, FET(Q2)(Q3)를 드라이브시키기 위해 별도로 와인딩(winding)을 할 필요가 없게 된다.In addition, since FETs Q2 and Q3 receive the output of the PWM IC 10 as a drive signal through the buffer 20, the circuit on the secondary side of the transformer T1 is driven in synchronization with the primary side, and the FET Q2 There is no need to wind separately to drive Q3.
이상에서와 같이 이 발명에 따른 DC-DC 콘버터에 의하면, 상기 트랜스의 2차측에 연결된 정류평활회로가2차측의 권선일측에 연결된 FET와, 이 FET 의 일측과 2차측 권선의 다른 일측간에 설치된 FET와, 이 FET로부터 출력되는 전압을 평활시키는 초크코일 및 콘덴서로 이루어지고, 상기 2단의 FET는 각기 버퍼의 출력에 게이트가 연결되고, 이버퍼은 상기 PWM IC의 출력에 연결된 것이므로 FET의 기생다이오드에 의해 스위칭의 오프시에도 초크코일에 축척된 에너지가 흐르게 되며, 내부저항이 매우 적은 소자로 회로가 구성되므로 드롭전압이 낮아 소자의 열발생이 적게 된다. 따라서 회로의 효율이 80∼90%로 증가되며, 버퍼에 의해 소자를 구동시키게 되므로 소자의 드라이브를 위해 별도의 와인딩이 필요하지 않게 되므로 장치의 부피가 감소된다.As described above, according to the DC-DC converter according to the present invention, a rectifier smoothing circuit connected to the secondary side of the transformer has a FET connected to one side of the secondary winding, and a FET provided between one side of the FET and the other side of the secondary winding. And a choke coil and a condenser for smoothing the voltage output from the FET. The two-stage FETs have their gates connected to the outputs of the buffers, and the buffers are connected to the outputs of the PWM ICs. As a result, the accumulated energy flows in the choke coil even when the switching is turned off, and since the circuit is composed of a device having a very low internal resistance, the drop voltage is low, thereby reducing the heat generation of the device. Therefore, the efficiency of the circuit is increased to 80-90%, and the device is driven by the buffer, so that a separate winding is not required for the drive of the device, thereby reducing the volume of the device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920011497A KR940008907B1 (en) | 1992-06-30 | 1992-06-30 | Dc-dc converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920011497A KR940008907B1 (en) | 1992-06-30 | 1992-06-30 | Dc-dc converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940001527A KR940001527A (en) | 1994-01-11 |
| KR940008907B1 true KR940008907B1 (en) | 1994-09-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920011497A KR940008907B1 (en) | 1992-06-30 | 1992-06-30 | Dc-dc converter |
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| Country | Link |
|---|---|
| KR (1) | KR940008907B1 (en) |
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1992
- 1992-06-30 KR KR1019920011497A patent/KR940008907B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR940001527A (en) | 1994-01-11 |
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