KR940008561B1 - Semiconductor integrated circuit - Google Patents

Abstract

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Description

Semiconductor integrated circuit

1 is a block circuit diagram showing a configuration of a conventional semiconductor integrated circuit for stepping down an external power supply voltage to make an internal power supply voltage of a low voltage.

2 is a layout view on a chip of a plurality of semiconductor circuits provided in a semiconductor integrated circuit.

FIG. 3 is a block circuit diagram showing a specific configuration example of the plurality of semiconductor circuits of FIG.

FIG. 4A is a circuit diagram showing an example of the configuration of the address buffer of FIG.

4B is a circuit diagram showing an example of the configuration of the predecoder of FIG.

5 is a block circuit diagram showing the configuration of a semiconductor integrated circuit of the present invention for stepping down an external power supply voltage therein to produce a low voltage internal power supply voltage.

FIG. 6 is a block circuit diagram showing a specific configuration example of the plurality of semiconductor circuits of FIG.

FIG. 7 is a circuit diagram showing the circuit configuration of the first embodiment of the voltage step down circuit in FIG.

FIG. 8 is a circuit diagram showing the circuit configuration of the second embodiment of the voltage step down circuit in FIG.

FIG. 9 is a circuit diagram showing the circuit arrangement of the third embodiment of the voltage step down circuit in FIG.

FIG. 10 is a block circuit diagram showing an embodiment in which the block circuit diagram of FIG. 6 is modified.

11 is a time-voltage characteristic diagram illustrating a stable state of an internal power supply voltage of a semiconductor integrated circuit of the present invention.

12 is a circuit diagram of another embodiment of a voltage step-down circuit.

13 to 19 are circuit diagrams showing specific circuit configurations of the step-down control circuit in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits that step down external power supply voltages to form internal power supply voltages.

In general, when semiconductor elements are miniaturized, the degree of integration of semiconductor integrated circuits is improved, which is preferable. On the other hand, when the semiconductor element is made finer, it is easy to cause an unfavorable state, such as insufficient internal pressure or susceptibility to high temperature electrons.

As a countermeasure for such an unfavorable state, the countermeasure which lowers the power supply voltage supplied to a semiconductor element and makes the electric field strength of each element part small is effective. As an example, the oxide film electric field strength can be lowered, thereby preventing the oxide film from aging. In addition, by reducing the channel electric field strength, the generation of high-temperature electrons can be suppressed to reduce the amount of high-temperature electrons injected into the oxide film, and so-called high-temperature electron instability (specifically fluctuation in threshold value Vth or deterioration of conductance) can be prevented. have.

As described above, lowering the power supply voltage can solve the problem of the miniaturization element. However, it is not preferable to prepare a dedicated external power supply because it complicates the system or requires a dedicated power supply line. Therefore, the external power supply voltage is stepped down inside the semiconductor integrated circuit, and a low voltage internal power supply voltage is made. 1 and 2 show the configuration of a conventional semiconductor integrated circuit in which the external power supply voltage is stepped down inside the semiconductor integrated circuit to create a low voltage internal power supply voltage.

In FIG. 1, VccPAD is a power supply terminal provided in a semiconductor chip, an external power supply is applied, A is a voltage step-down circuit, and C11-C1n represents a plurality (n) of semiconductor circuits. As shown in FIG. 2, one power supply terminal VccPAD is normally provided on the semiconductor chip 2, and the semiconductor circuits C11-C1n are arranged on the semiconductor chip 2 in a planar two-dimensional manner. The power supply step down circuit A makes the internal power supply voltage Vint by stepping down the external power supply voltage applied to the power supply terminal VccPAD to a predetermined voltage. This external voltage is a common power supply voltage applied to other semiconductor integrated circuits, for example, + 5V. Step-down to a predetermined voltage is performed using the channel resistance of a MOS transistor, for example.

Here, the predetermined voltage is a voltage required for the operation of the agitated semiconductor element (for example, MOS transistor) constituting the plurality of internal semiconductor circuits C11-C1n, and is a low voltage effective for avoiding breakdown voltage and high temperature electrons.

3 shows an example of a specific circuit of the semiconductor circuits C11-C1n in FIG. 1 when the semiconductor integrated circuit is a dynamic RAM. In the figure, C ₁₁ is a mode control circuit, C ₁₂ is a refresh address counter, C ₁₃ is an address buffer, C ₁₄ is a predecoder, C ₁₅ is a basic bias generation circuit, C ₁₆ is a sense amplifier driver, and C ₁₇ is a first clock generating circuit, C ₁₈ is a gate circuit, C ₁₉ is the second clock generating circuit, C ₂₀ is sseoneotgi clock generating circuit, C ₂₁ is the column D. Koh more, C ₂₂ is the low-di Koh more, C ₂₃ is a data input buffer, C ₂₄ is a data output buffer, and each of these semiconductor circuits C ₁₁ -C ₂₄ is configured to supply an internal power supply voltage stepped down by the step-down circuit A. 4A is a circuit diagram showing an example of the configuration of the address buffer of FIG. 3, and FIG. 4B is a circuit diagram showing an example of the configuration of the predecoder of FIG.

However, in such a conventional semiconductor integrated circuit, a plurality of internal semiconductor circuits (C11-C1n in FIG. 1 and C ₁₁ -C _{1n in} FIG. 3) share one internal power supply voltage Vint. Among the semiconductor circuits (C11-C1n in FIG. 1 and C ₁₁ -C _{1n in} FIG. 3), the potential of Vint drops instantaneously during operation of a semiconductor circuit that consumes a large current. The circuit may malfunction.

Therefore, a circuit for detecting the voltage drop of the internal power supply voltage Vint is provided, and a relatively large current is supplied at the time of detecting the voltage drop to suppress the fluctuation of the internal power supply voltage. In this method, however, a certain response delay cannot be avoided from the time when the actual voltage drop occurs until the current is supplied, which effectively suppresses the instantaneous voltage drop of the internal power supply voltage Vint. Was not enough.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of effectively suppressing a voltage fluctuation of an internal power supply voltage even when a semiconductor circuit consuming a large current is operated, and there is no fear that the semiconductor circuit will malfunction.

In order to achieve the above object, the present invention collects the external power supply voltage existing outside the semiconductor chip with the external power supply terminal interposed therebetween, stepping down the external power supply voltage by a voltage stepping means provided inside the semiconductor chip, Next to the semiconductor integrated circuit supplied as a voltage inside the semiconductor chip, a plurality of voltage step-down means connected to an external power supply terminal inside the semiconductor chip to change the external power supply voltage to a desired internal power supply voltage are provided. Each of them is characterized in that at least one of a plurality of semiconductor circuit blocks made inside the semiconductor chip is connected.

As a result, in the present invention, a dedicated internal power supply voltage is generated for each of several semiconductor circuits, and when a change occurs in one internal power supply voltage, the influence on the other internal power supply voltage is eliminated.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated based on drawing.

5 is a block circuit diagram showing the configuration of a semiconductor integrated circuit according to the present invention. In Fig. 5, VccPAD denotes a power supply terminal for an external power source, A1-An denotes a voltage step-down circuit, and C11-C1n denotes a semiconductor circuit block, respectively. The voltage step-down circuits A1-An are made for each of the plurality of semiconductor internal circuits (semiconductor circuit blocks) C11-C1n, and the predetermined voltage resistance is applied to the external power supply voltage Vcc applied to the power supply terminal VccPAD, for example, using a channel resistance of the MOS transistor. Step down to the voltage and make an internal power supply voltage of Vint1-Vintn respectively.

Here, the plurality of semiconductor circuit blocks C11-C1n are respective functional blocks formed in a semiconductor integrated circuit. For example, in a dynamic RAM (DRAM), a functional block such as a clock generator or a memory cell array (including a sense amplifier) is a semiconductor circuit. It is a block. FIG. 6 shows a specific circuit example of the semiconductor circuits C11-C1n in the case where the semiconductor integrated circuit is a DRAM, and the same reference numerals are given to the same parts as the conventional semiconductor integrated circuit shown in FIG. In FIG. 6, C ₁₁ is a mode control circuit, C ₁₂ is a refresh address counter, C ₁₃ is an address buffer, C ₁₄ is a predecoder, C ₁₅ is a basic bias generation circuit, C ₁₆ is a sense amplifier driver, and C ₁₇ is a first circuit clock generation, C ₁₈ is a gate circuit, C ₁₉ is the second clock generating circuit, C ₂₀ is sseoneotgi clock generating circuit, C ₂₁ is the column D. Koh more, C ₂₂ is the low-di Koh more, C ₂₃ is a data input The buffer C ₂₄ is a data output buffer, and each of these semiconductor circuits C ₁₁ -C ₂₄ is supplied with an internal power supply voltage stepped down by the step-down circuits A1-A5. The address buffers C ₁₃ and predecoder C ₁₄ have the same configurations as shown in FIGS. 4A and 4B.

In this DRAM, in this embodiment, the mode control circuit C ₁₁ , the refresh address counter C ₁₂ , the address buffer C ₁₃ , the predecoder C ₁₄ , the basic bias generator circuit C ₁₅ and the low decoder C ₂₂ are semiconductors of FIG. 5. Corresponds to the circuit C11, and operates by the internal power supply voltage Vint1 by the step-down circuit A1. The sense amplifier driver C ₁₆ corresponds to the semiconductor circuit C ₁₂ in FIG. 5 and operates by the internal power supply voltage Vint2 by the step-down circuit A2. In addition, the first clock generating circuit C ₁₇ , the gate circuit C ₁₈ , the second clock generating circuit C ₁₉ and the column decoder C ₂₁ correspond to the semiconductor circuit C ₁₃ of FIG. 5, and the internal power supply voltage Vint3 by the step-down circuit A3. It works by Similarly, the data input buffer C ₂₃ and the data output buffer C _{24 correspond} to the semiconductor circuit C ₁₄ , operate by the internal power supply voltage Vint4 by the step-down circuit A4, and the write clock generation circuit C ₂₀ corresponds to the semiconductor circuit C ₁₅ . It operates by the internal power supply voltage Vint5 by the step-down circuit A5.

In general, in DRAM, the operating current of the memory cell array including the sense amplifier is extremely large, so that the current flowing through the step-down circuit A1 increases during the operation of the memory cell array, resulting in a manual voltage drop in the internal power supply voltage Vint1. In this embodiment, since the internal power supply voltage Vint1 and the internal power supply voltages Vint2-Vint5 of the other semiconductor circuits C ₁₂ -C ₁₅ are independent of each other, even when a voltage drop occurs in one internal power supply voltage Vint1, another internal power supply voltage The voltage drop of Vint2-Vint5 can be suppressed.

7 to 9 show the structure of another embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 7 shows an example in which the voltage step-down means A11-A1n formed for each of the plurality of semiconductor circuit blocks C11-C1n are each composed of MOS transistors. In this example, the MOS transistor is connected to the external power supply terminal VccPAD with the common line L interposed therebetween, and the gate of each MOS transistor is also connected to the external power supply terminal VccPAD with the common line L interposed therebetween. In addition, the resistors R1-Rn interposed in the common line L represent the wiring resistance interposed between the power supply terminal VccPAD and each MOS transistor. In this embodiment, each internal power supply voltage Vint2-Vintn is stepped down in the channel resistance of the MOS transistor with respect to the power supply voltage Vcc.

FIG. 8 shows another example in which the voltage step-down means A11-A1n formed for each of the plurality of semiconductor circuit blocks C11-C1n are each composed of MOS transistors, and the same components as in FIG. 7 are denoted by the same reference numerals. In this example, the drain of each MOS transistor is connected to the external power supply terminal VccPAD with the first common line L1 interposed, and the gate of each MOS transistor is connected to the external power supply terminal VccPAD with the second common line L2 interposed therebetween. It is. In addition, the resistors R1-Rn interposed between the first common lines L1 represent wiring resistances interposed between the power supply terminal VccPAD and each MOS transistor.

According to the structure like FIG. 8, the following effect is acquired. In other words, in the case where power is supplied from one external power terminal VccPAD to several semiconductor circuits arranged on the chip, this arrangement is a planar two-dimensional arrangement as shown in FIG. The wiring length between the semiconductor circuits is different, and hence the wiring resistance is also different. This is represented schematically by the resistors R1-Rn in FIG.

If current of ImA flows through C1n at the last end of the first common line L1, the potential VN ₁ , VN ₂ , ... VN _n of each node N1 ... Nn of the first common line L1 It is expressed by each expression.

VN ₁ = Vcc-V _R1

VN ₂ = Vcc- (V _R1 + V _R2 )

VN _n = Vcc- (V _R1 + V _R2 + ... V _Rn )

Vcc: External power supply voltage

V _R1 : Voltage drop by R1 (I · R1)

V _R2 : Voltage drop by R2 (I · R2)

V _Rn : Voltage drop due to Rn (I / Rn)

This voltage drop R _R1 , R _R2 ... R _Rn is given as the accumulation value (multiplied value) of the current ImA and the resistance R1 (or R2 ... Rn), so that a large current (a When ImA) flows in, other semiconductor circuits C11, C12 ... are affected by the voltage drop V _R1 , R _R2 .

However, in this embodiment, the gates of the MOS transistors connected to each node N1 ... Nn are connected to the external power supply terminal VccPAD by the second common line L2, which is a dedicated wiring separate from the first common line L1. Because we connected

(i) The gate current of the MOS transistors is extremely small (although it is almost zero), so that the gate potential of each MOS transistor can be made almost the external power supply potential Vcc potential.

(ii) Therefore, even if a voltage drop occurs at the nodes N1 ... Nn, the internal power supply voltage Vint1 ... Vintn supplied to the semiconductor circuits C11 ... C1n is equal to the threshold Vth of the MOS transistor at the external power supply potential Vcc. Can be reduced to a constant potential,

(iii) The influence of the voltage drop due to the wiring resistances R1 ... Rn of the first common line L1 can be effectively avoided.

That is, as shown in FIG. 11, the external power supply potential Vcc is given a voltage as low as the threshold value Vth of the MOS transistor, for example, the internal power supply voltage Vint2 of the semiconductor circuit C12 is, for example, at a time t1, the potential VN2 of the node N2 is equal to the potential difference ΔVN2. Even if it decreases by, the gate potential of the MOS transistor is almost maintained at the external power supply potential Vcc by the second common line L2, which is a dedicated wiring, and is not affected by the above-described potential difference? The degree is small so that a nearly constant potential (Vcc-Vth) can be maintained. In addition, the broken line in FIG. 11 is the voltage waveform of FIG. 7 connected to the same node in common with the gate-drain of a MOS transistor, and the internal power supply voltage Vint2 is fluctuate | varied fluctuation | variation by the voltage change of a node.

9 shows a modification of the embodiment of FIG. 8, and like reference numerals denote the same components as those in FIG. In this embodiment, the gates of the respective MOS transistors constituting the voltage step-down circuits A11-A1n are connected to the second common line L2 with the step-down control circuits G1, G2 ... Gn interposed therebetween. In this embodiment, when any of the step-down control circuits G1 ... Gn, for example, G2 is operated by the individual selection signals S1 ... Sn, the second common control is provided with the step-down control circuit G2 in operation. The line L2 and the gate of the MOS transistor A12 are connected so that the gate potential of the MOS transistor can be maintained at almost the power supply voltage Vcc, and the same effect as the embodiment shown in FIG. 8 is obtained. Further, in this embodiment, the power supply to each semiconductor circuit block C11-C1n can be turned on / off by the individual selection signals S1-Sn. For example, the memory cell array is divided into a plurality of blocks, and the power supply of the non-operation block is supplied. It is preferable to apply to a semiconductor integrated circuit of a type that reduces power by turning off.

FIG. 10 shows an embodiment in which a specific circuit example of the semiconductor circuits C11-C1n of the present invention is modified in the case where the semiconductor integrated circuit shown in FIG. 6 is DRAM. The data input buffer C ₂₃ and the data output buffer C ₂₄ are shown in FIG. This is an example of using a device that wants to apply an external power source that is not stepped down due to the characteristics of the device. In the semiconductor integrated circuit of the present invention, a step-down circuit is provided for each of the semiconductor circuits, and thus a modification in consideration of the characteristics of the device is possible. In the circuit of FIG. 10, the internal power supply voltage of the sense amplifier driver C ₁₆ is generated by the step-down circuit A2. However, it is not necessary to provide this step-down circuit A2 when the sense amplifier driver itself has a step-down action of the external power supply voltage. .

12 shows a circuit diagram of another embodiment of the voltage step-down circuit used in the above-described embodiment, and is an example in which a voltage step-down circuit is formed using a plurality of MOS transistors.

13 and 14 are circuit diagrams showing a specific circuit configuration example of the step-down control circuit in FIG. 9, and are examples of the case where the step-down potential is the external power supply voltage Vcc threshold voltage Vth. Therefore, when the external power supply voltage Vcc is 5V, the threshold voltage is about 1V, so the internal power supply voltage in the semiconductor integrated circuit using the circuit of this embodiment becomes about 4V.

15 to 18 are circuit diagrams showing another specific circuit configuration example of the step-down control circuit in Fig. 9, and the step-down potential is an example in which the external power supply voltage Vcc threshold voltage is 2Vth. Therefore, when the external power supply voltage Vcc is 5V, the threshold voltage is about 1V, so the internal power supply voltage in the semiconductor integrated circuit using the circuit of this embodiment becomes about 3V.

19 is a circuit diagram showing another specific circuit configuration example of the step-down control circuit in FIG. 9, and shows a circuit configuration in which the step-down potential can be arbitrarily set.

Claims (10)

The external power supply voltage present outside the semiconductor chip is collected with the external power supply terminal VccPAD interposed therebetween, and the voltage is lowered by the voltage step-down means A provided inside the semiconductor chip. In a semiconductor integrated circuit supplied inside a semiconductor chip, a plurality of voltage step-down means (A1-A1n) connected to the external power supply terminal (VccPAD) inside the semiconductor chip and changing an external power supply voltage to a desired internal power supply voltage. And at least one of a plurality of semiconductor circuit blocks (C11-C1n) provided inside each semiconductor chip is connected to each of the voltage dropping means (A1-An). The semiconductor integrated circuit according to claim 1, wherein the voltage dropping means (A1-An) for each of the semiconductor circuit blocks (C11-C1n) include at least one MOS transistor (A11-A1n). The gate of each of the MOS transistors A11-A1n, wherein the drains of the MOS transistors A11-A1n are connected in common with a first common line and connected to the external power supply terminal VccPAD. The semiconductor integrated circuit is configured to be connected to the first common line. The gate of each of the MOS transistors A11-A1n, wherein the drains of the MOS transistors A11-A1n are connected in common with a first common line and connected to the external power supply terminal VccPAD. And a common connection via a second common line to connect to the external power supply terminal (VccPAD). 5. The power supply to each of the semiconductor circuit blocks C11-C1n according to claim 4, wherein a separate selection signal S1-Sn is applied between the gates of the MOS transistors A11-A1n and the second common line. A semiconductor integrated circuit comprising a step-down control circuit (G1-Gn) that can be turned on and off independently. 6. The semiconductor integrated circuit according to claim 5, wherein the voltage dropping means (A1-An) for each of the semiconductor circuit blocks (C11-C1n) include at least one MOS transistor (A11-A1n). 7. The semiconductor integrated circuit according to claim 6, wherein an external power supply voltage is stepped down by a threshold level of the MOS transistor by the step-down control circuits (G1-Gn) and the voltage step-down means (A1-An). 7. The semiconductor integrated circuit according to claim 6, wherein the external power supply voltage is stepped down by twice the threshold level of the MOS transistor by the step-down control circuits G1-Gn and the voltage step-down means A1-An. . 7. The semiconductor integrated circuit according to claim 6, wherein an external power supply voltage is stepped down by an arbitrary voltage by each step-down control circuit (G1-Gn) and voltage step-down means (A1-An). The voltage reduction means A1-An of the step-down control circuits G1-Gn and the step-down values of the external power supply voltages of the respective semiconductor circuit blocks C11-C1n are not all the same. A semiconductor integrated circuit characterized by.