KR940008506A

KR940008506A - Input level display circuit of satellite broadcasting receiver

Info

Publication number: KR940008506A
Application number: KR1019920017352A
Authority: KR
Inventors: 우경일
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1992-09-23
Filing date: 1992-09-23
Publication date: 1994-04-29

Abstract

본 발명은 DBS(DIRECT BOADCASTING BY SATELLITE)의 실시에 따라 위성 방송 수신기의 설치시에 이용될수 있는 입력신호 레벨 표시 회로에 관한 것으로, 위성 방송 수신 안테나(1)로 부터의 수신 신호를 입력받는 튜너(TUNER)(2)과, 상기 튜너(2)의 검파 출력 단자로부터의 복합 영상 신호(COMPOSITE VIDEO SIGNAL)를 전송하는 버퍼(3)와, 상기 버펀(3)를 통해 영상 신호를 입력받아 잡음을 검출해 내고 검출된 잡음 신호를 적분하여 직류 전압으로 만드는 잡음 검출 회로 수단(4)과, 상기 잡음 검출 회로수단(4)을 통해 출력되는 아날로그 직류 전압을 디지탈 신호로 변환하는 A/D변환수단(7)과, 상기 A/D변환수단(7)에 의해 변환된 디지탈 신호를 입력으로 하여 신호를 읽어내는 마이컴(8)과, 상기 마이컴(8)에 의해 읽혀진 신호를 표시해 주기 위한 표시수단(9)과, 상기 버퍼(3)를 통한 정상 신호를 영상 처리하는 영상 처리 회로 수단(5)과, 상기 버퍼(3)에 의해 전송된 신호를 인가받아 음성 처리하는 음성 처리 회로 수단(6)을 구비한 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal level display circuit that can be used when installing a satellite broadcasting receiver according to the implementation of DIRECT BOADCASTING BY SATELLITE (DBS), and further comprising: a tuner for receiving a reception signal from the satellite broadcasting reception antenna 1; TUNER (2), a buffer (3) for transmitting a composite video signal from the detection output terminal of the tuner (2), and a video signal through the buffer (3) to detect noise Noise detection circuit means 4 for integrating the detected noise signal to a DC voltage, and A / D conversion means 7 for converting an analog DC voltage output through the noise detection circuit means 4 into a digital signal. ), A microcomputer 8 for reading out the signal by inputting the digital signal converted by the A / D conversion means 7, and display means 9 for displaying the signal read by the microcomputer 8; And normal through the buffer (3) And image processing circuit means (5) for image processing a signal, and audio processing circuit means (6) for receiving a signal transmitted by the buffer (3) and performing audio processing.

Description

Input level display circuit of satellite broadcasting receiver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 발명의 위성 수신기의 블럭 구성도.1 is a block diagram of a satellite receiver of the present invention.

제2도는 잡음 검출회로부의 상세 회로도.2 is a detailed circuit diagram of a noise detection circuit portion.

Claims

A tuner 2 for receiving the received signal from the satellite broadcast receiving antenna 1 and a buffer for transmitting a composite video signal from the detection output terminal of the tuner 2; And noise detection circuit means 4 for inputting an image signal through the buffer 3 to detect noise, and integrating the detected noise signal into a DC voltage, and through the noise detection circuit means 4. An A / D conversion means (7) for converting the output analog DC voltage into a digital signal, a microcomputer (8) for reading out a signal as the input of the digital signal changed by the A / D conversion means (7), and Display means 9 for displaying a signal read by the microcomputer 8, image processing circuit means 5 for image processing a settled signal through the buffer 3, and the buffer 3 Speech processing circuit means (6) for receiving a signal and processing speech; An input level display circuit of a phase broadcast receiver.

※ Note: The disclosure is based on the initial application.