KR940008464A - Digital copy protection circuit - Google Patents
Digital copy protection circuit Download PDFInfo
- Publication number
- KR940008464A KR940008464A KR1019920017553A KR920017553A KR940008464A KR 940008464 A KR940008464 A KR 940008464A KR 1019920017553 A KR1019920017553 A KR 1019920017553A KR 920017553 A KR920017553 A KR 920017553A KR 940008464 A KR940008464 A KR 940008464A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- copy protection
- counter
- edge
- reset
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
- H04N5/913—Television signal processing therefor for scrambling ; for copy protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
본 발명은 영상처리장치의 복사 방지 회로에 관한 것으로 본 발명의 영상신호처리장치의 디지탈 복사 방지 회로는, 1필드마다 헤드 스위치 에지펄스를 발생시키기 위한 에지펄스 발생부와 복사 방지 신호의 위치를 카운트하여 상기 복사 방지 신호의 위치만을 리셋시키는 리셋 펄스 발생부와 상기 리셋 펄스 발생 구간에서 복사 방지 신호를 검출하기 위한 복사 방지 신호 검출부 및 상기 복사 방지 신호 검출부로부터 검출신호가 발생하면 영상신호의 출력을 방지하는 킬러신호를 발생하기 위한 킬러 신호 발생부를 구비하여 이루어지는 것을 특징으로 한다. 따라서 본 발명의 디지탈 복사 방지 회로는 회로의 모든 부분을 디지탈화 함으로써 집적도를 향상시키고 영상처리 시스템의 기록매체에 대한 무단복사를 방지할 수 있다.The present invention relates to a copy protection circuit of an image processing apparatus. The digital copy protection circuit of the image signal processing apparatus of the present invention counts the position of an edge pulse generator and a copy protection signal for generating a head switch edge pulse for each field. A reset pulse generator for resetting only the position of the copy protection signal, a copy protection signal detector for detecting a copy protection signal in the reset pulse generation section, and a detection signal generated from the copy protection signal detector to prevent the output of an image signal. And a killer signal generator for generating a killer signal. Therefore, the digital copy protection circuit of the present invention can improve the degree of integration and prevent unauthorized copying of the recording medium of the image processing system by digitalizing all parts of the circuit.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 영상처리장치의 복사방지신호의 파형을 나타내는 파형도.1 is a waveform diagram showing waveforms of a copy protection signal of an image processing apparatus.
제2도는 영상처리장치의 한 필드에서 복사 방지 신호의 위치를 나타내는 예시도.2 is an illustration showing the position of the copy protection signal in one field of the image processing apparatus.
제3도는 본 발명에 따른 영상처리장치의 디지탈 복사 방지 회로의 블럭도.3 is a block diagram of a digital copy protection circuit of an image processing apparatus according to the present invention.
제4도는 본 발명의 일실시예로서 제3도의 에지 펄스발생부의 구체적인 회로도.4 is a detailed circuit diagram of an edge pulse generator of FIG. 3 as an embodiment of the present invention.
제5도는 본 발명의 일실시예로서 제3도의 리셋 펄스 발생부의 구체적인 회로도.FIG. 5 is a detailed circuit diagram of the reset pulse generator of FIG. 3 as an embodiment of the present invention. FIG.
제6도는 본 발명의 일실시예로서 제3도의 복사 방지 검출신호 발생부의 구체적인 회로도.6 is a detailed circuit diagram of the copy protection detection signal generator of FIG. 3 as an embodiment of the present invention.
제7도는 본 발명의 일실시예로서 제3도의 킬러 신호 발생부의 구체적인 회로도.7 is a detailed circuit diagram of a killer signal generator of FIG. 3 as an embodiment of the present invention.
제8도는 제4, 5, 6도 및 제7도의 출력을 나타내는 출력 파형도.8 is an output waveform diagram showing the outputs of FIGS. 4, 5, 6 and 7;
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920017553A KR100189962B1 (en) | 1992-09-25 | 1992-09-25 | Digital circuit for preventing illegal dubbing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920017553A KR100189962B1 (en) | 1992-09-25 | 1992-09-25 | Digital circuit for preventing illegal dubbing |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940008464A true KR940008464A (en) | 1994-04-29 |
KR100189962B1 KR100189962B1 (en) | 1999-06-01 |
Family
ID=19340124
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920017553A KR100189962B1 (en) | 1992-09-25 | 1992-09-25 | Digital circuit for preventing illegal dubbing |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100189962B1 (en) |
-
1992
- 1992-09-25 KR KR1019920017553A patent/KR100189962B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100189962B1 (en) | 1999-06-01 |
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