KR940008215A - Sinusoidal wave generation circuit - Google Patents
Sinusoidal wave generation circuit Download PDFInfo
- Publication number
- KR940008215A KR940008215A KR1019920017926A KR920017926A KR940008215A KR 940008215 A KR940008215 A KR 940008215A KR 1019920017926 A KR1019920017926 A KR 1019920017926A KR 920017926 A KR920017926 A KR 920017926A KR 940008215 A KR940008215 A KR 940008215A
- Authority
- KR
- South Korea
- Prior art keywords
- input
- nhz
- wave
- generation circuit
- control
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
본 발명은 직류전원을 교류로 변환하는 인버터(역변환기)의 제어회로에 있어서 4개의 제어입력을 갖는 8채널 멀티플렉서의 입력측에 계단식 정현파레벨 전압발생회로를, 출력측에 능동필터를 연결하고 제어입력측에는 리셋트 펄스, 16×NHz의 클락펄스 및 업다운 신호인 NHz의 구형파가 입력되는 BCD 업다운카운터로 회로를 구성하여 비반전 입력 Vc로 조정함에 있어서 신호파인 정현파의 진폭의 크기를 용이하게 조정할 수 있는 것이다.The present invention provides a stepped sinusoidal level voltage generation circuit at the input side of an eight-channel multiplexer having four control inputs in a control circuit of an inverter (inverter converter) for converting a DC power source into an alternating current, an active filter connected to the output side, and a control input side It is easy to adjust the amplitude of the sine wave, which is a signal wave, by adjusting the non-inverting input Vc by constructing a circuit with a BCD up-down counter to which a reset pulse, a clock pulse of 16 x NHz, and a square wave of NHz, which is an up-down signal, are input. .
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 블록 다이어그램.2 is a block diagram of the present invention.
제3도는 본 발명의 회로도.3 is a circuit diagram of the present invention.
제5도는 계단식 정현파 레벨전압 발생회로.5 is a stepped sinusoidal level voltage generation circuit.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920017926A KR950009125B1 (en) | 1992-09-30 | 1992-09-30 | Symmetric wave developing circuit with variable width |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920017926A KR950009125B1 (en) | 1992-09-30 | 1992-09-30 | Symmetric wave developing circuit with variable width |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940008215A true KR940008215A (en) | 1994-04-29 |
KR950009125B1 KR950009125B1 (en) | 1995-08-14 |
Family
ID=19340394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920017926A KR950009125B1 (en) | 1992-09-30 | 1992-09-30 | Symmetric wave developing circuit with variable width |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950009125B1 (en) |
-
1992
- 1992-09-30 KR KR1019920017926A patent/KR950009125B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950009125B1 (en) | 1995-08-14 |
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Legal Events
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060804 Year of fee payment: 12 |
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LAPS | Lapse due to unpaid annual fee |