KR940007394B1 - Trench type eprom cell and faricating method thereof - Google Patents
Trench type eprom cell and faricating method thereof Download PDFInfo
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- KR940007394B1 KR940007394B1 KR1019910012954A KR910012954A KR940007394B1 KR 940007394 B1 KR940007394 B1 KR 940007394B1 KR 1019910012954 A KR1019910012954 A KR 1019910012954A KR 910012954 A KR910012954 A KR 910012954A KR 940007394 B1 KR940007394 B1 KR 940007394B1
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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Abstract
Description
제 1 도는 종래의 스택형 EPROM 구조를 도시한 단면도.1 is a cross-sectional view showing a conventional stacked EPROM structure.
제 2 도는 종래의 스플리트 게이트(split gate)형 EPROM 구조를 도시한 단면도.2 is a cross-sectional view showing a conventional split gate type EPROM structure.
제 3 도는 본 발명의 트렌치형 EPROM 셀을 배열한 레이아웃트 도면.3 is a layout diagram of an arrangement of trench type EPROM cells of the present invention.
제3a도는 내지 제3h도는 본 발명에 의해 트렌치형 EPROM 제조단계를 도시한 단면도.3a to 3h are cross-sectional views showing a trench type EPROM manufacturing step according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형 기판 2 및 3 : 공통소오스용 N-층 및 N+층1: P type substrate 2 and 3: N - layer and N + layer for common source
4 : 필드산화막 5 : 자연산화막4: field oxide film 5: natural oxide film
6 : P+영역 7 : 드레인용 N+영역6: P + region 7: N + region for drain
8 : 버리드 산화막 9 : 트렌치8: Burd oxide film 9: Trench
10 및 21 : 제 1 절연층 11 : 플로팅 게이트용 제 1 폴리실리콘층10 and 21: first insulating layer 11: first polysilicon layer for floating gate
11A 및 22 : 플로팅 게이트 12 및 23 : 제 2 절연층11A and 22: floating gates 12 and 23: second insulating layer
13 : 제어게이트용 제 2 폴리실리콘층13: second polysilicon layer for control gate
13A 및 24 : 제어게이트 20 : 기판13A and 24: control gate 20: substrate
25 : 드레인 26 : 소오스25: drain 26: source
30 : 비트라인 31 : 워드라인30: bit line 31: word line
32 : 트렌치영역32: trench area
본 발명은 고집적 반도체 소자의 트렌치형 EPROM셀 및 그 제조방법에 관한 것으로 특히 집적도를 향상시키며 전류이동능력 및 프로그램 특성을 향상시킬 수 있도록 기판에 수직방향의 채널 형상을 갖는 트렌치형 EPROM셀 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench type EPROM cell of a highly integrated semiconductor device and a method of manufacturing the same. In particular, a trench type EPROM cell having a channel shape in a direction perpendicular to a substrate can be improved to improve integration density and improve current transfer capability and program characteristics. It is about a method.
일반적으로 플레쉬(Flash) EPROM셀의 구조는 제 1 도에 도시한 바와 같이 스택형 EPROM셀로서 기판(20) 상부면의 예정된 영역에 소오스(26) 및 드레인(25)이 형성되어 기판에 수평방향으로 채널영역이 구성되고, 채널영역 상부에 플로팅 게이트(22)와 제어게이트(24)가 제 1 절연층(21) 및 제 2 절연층(23)에 의해 절연된 상태로 적층되어 구성되는데 집적도가 높아질수록 EPROM셀 특성의 문제점이 발생된다.In general, the structure of a flash EPROM cell is a stacked EPROM cell, in which a source 26 and a drain 25 are formed in a predetermined area of an upper surface of the substrate 20, as shown in FIG. The channel region is formed, and the floating gate 22 and the control gate 24 are stacked in an insulated state by the first insulating layer 21 and the second insulating layer 23 on the channel region. The higher the problem of EPROM cell characteristics.
또한, 제 2 도의 스플리트 게이트 EPROM셀도 상기 스택형 EPROM셀과 마찬가지로 기판(20) 상부면에 형성된 소오스(26)와 드레인(25) 사이에서 수평방향으로 채널영역이 형성되는데 스택형 EPROM셀과 다른 구조는 플로팅 게이트(22) 상부면에 위치하는 제어게이트(24A)가 플로팅 게이트(22) 일측면의 예정된 영역의 기판(20) 상부까지 덮고 있다는 것이다. 그러나, 이 스플리트 게이트형 EPROM셀 구조도 집적도가 높아질수록 셀의 면적이 줄어들게 되므로 셀 특성이 저하되는 문제점이 있다.In addition, similarly to the stacked EPROM cell, the split gate EPROM cell of FIG. 2 also has a channel region formed in a horizontal direction between the source 26 and the drain 25 formed on the upper surface of the substrate 20. Another structure is that the control gate 24A located on the top surface of the floating gate 22 covers the top of the substrate 20 in a predetermined area on one side of the floating gate 22. However, this split gate type EPROM cell structure also has a problem that the cell area is reduced as the degree of integration decreases.
따라서, 본 발명은 집적도가 증가되어도 셀 특성이 저하되지 않도록 하기 위하여 EPROM의 채널영역을 기판에 대하여 수평방향에서 수직방향 구조로 변경한 트렌치형 EPROM셀 및 그 제조방법을 제공하는데 목적이 있다.Accordingly, an object of the present invention is to provide a trench type EPROM cell in which the channel region of the EPROM is changed from a horizontal direction to a vertical structure with respect to the substrate so that the cell characteristics do not deteriorate even when the degree of integration is increased.
본 발명의 EPROM셀 구조는 P형 기판 하부면에 공통소오스용 저농도 N-층과 고농도 N+층이 순차적으로 형성되고, P형 기판 상부면에 P+영역과 드레인용 고농도 N+영역이 순차적으로 형성되고, 드레인용 고농도 N+영역 상부에 베리드 산화막이 형성되고 상기 베리드 산화막, 드레인용 고농도 N+영역, 고농도 P+영역, P형기판, 저농도 N-층의 예정된 부분이 식각되어 트렌치가 형성되고, 상기 트렌치 표면에 제 1 절연층이 형성되고, 제 1 절연층과 베리트 산화막 상부에 플로팅 게이트, 제 2 절연층 및 제어게이트가 순차적으로 형성되고, 상기 제어게이트 전압에 의해 트렌치 벽면의 P형 기판에 채널영역이 형성되는 것을 특징으로 한다.In the EPROM cell structure of the present invention, a low concentration N − layer and a high concentration N + layer for a common source are sequentially formed on a lower surface of a P type substrate, and a P + region and a high concentration N + region for drain are sequentially formed on an upper surface of a P type substrate. formed is, the buried oxide film on the upper drain high-concentration N + region is formed in the buried oxide layer, a drain high-concentration N + region, high concentration P + region, P-type substrate, a lightly doped N - a predetermined portion of the layer is etched a trench A first insulating layer is formed on the trench surface, and a floating gate, a second insulating layer, and a control gate are sequentially formed on the first insulating layer and the barrier oxide film, and the P of the trench wall is formed by the control gate voltage. The channel region is formed on the type substrate.
본 발명의 EPROM셀 제조방법에 의하면 P형 기판 하부면에 공통소오스용 저농도 N-층과 고농도 N+층을 에피택셜 성장법에 의해 각각 형성하는 단계와, P형 기판 상부면의 예정된 부분에 필드산화막을 형성하는 단계와, 필드산화막이 없는 P형 기판 상부면의 예정된 고농도의 P형 불순물을 주입하여 P+영역을 형성하고, 다시 고농도의 N형 불순물을 주입하여 드레인용 N+영역을 P+영역내의 상부에 형성하는 단계와, 드레인용 N+영역 상부면에 베리드 산화막을 성장시킨 다음, 트렌치 마스크를 이용하여 예정된 부분의 베리드 산화막, 드레인용 N+영역, P+영역, P형 기판, 공통소오스용 N-층을 순차적으로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치 표면상에 제 1 절연층을 형성하고, 제 1 절연층 상부면에 플로팅 게이트용 폴리실리콘층을 증착한 다음, 패턴공정으로 플로팅 게이트를 형성하는 단계와, 상기 플로팅 게이트 상부면에 제 2 절연층을 형성하고, 제 2 절연층 상부면에 제어게이트용 폴리실리콘층을 증착한 다음, 패턴공정으로 제어게이트를 형성하는 단계로 이루어지는 것을 특징으로 한다.According to the EPROM cell manufacturing method of the present invention, a step of forming a low concentration N − layer and a high concentration N + layer for a common source on the lower surface of the P-type substrate by epitaxial growth method, and a field on a predetermined portion of the upper surface of the P-type substrate a step of forming an oxide film, and a predetermined high concentration of the P-type implanting impurities to form a P + region, drain again injected at a high concentration N-type impurity incorporated N + region of the upper surface P-type substrate with no field oxide film P + Forming a buried oxide film on the upper surface of the drain N + region, and then forming a buried oxide film, a drained N + region, a P + region, and a P-type substrate in a predetermined portion using a trench mask. Forming a trench by sequentially etching the N - layer for common source, forming a first insulating layer on the trench surface, and depositing a polysilicon layer for floating gate on the upper surface of the first insulating layer Next, forming a floating gate by a pattern process, forming a second insulating layer on an upper surface of the floating gate, depositing a polysilicon layer for a control gate on an upper surface of the second insulating layer, and then controlling the gate by a pattern process Characterized in that it comprises a step of forming.
이하, 첨부된 도면을 참조하여 본 발명의 트렌치형 EPROM셀의 제조방법을 상세히 설명하고자 한다.Hereinafter, a method of manufacturing a trench type EPROM cell of the present invention will be described in detail with reference to the accompanying drawings.
제 3 도는 본 발명의 트렌치형 EPROM셀을 배열한 레이아웃트 도면으로서, 제어게이트용 워드라인(31), 드레인용 비트라인(30), 트렌치영역(32)이 도시되는데 비트라인(30)은 콘택이 없는 구조이다.3 is a layout diagram of trench type EPROM cells of the present invention, in which a control gate word line 31, a drain bit line 30, and a trench region 32 are shown. The bit line 30 is a contact. There is no structure.
제3a도 내지 제3h도는 본 발명의 제조방법에 의해 트렌치형 EPROM셀을 제조하는 단계를 제 3 도의 A-A' 단면을 도시한 것이다.3A to 3H show a cross-sectional view taken along the line A-A 'of FIG. 3, in which a trench type EPROM cell is manufactured by the manufacturing method of the present invention.
제3a도는 P형 기판(1) 하부에 저농도 N-층(2)을 에피택셜 성장법으로 성장시키고, 저농도 N-층(2) 하부에 고농도 N+층(3)을 에피택셜 성장법으로 성장시킨 상태의 단면도로서, 저농도 N-층(2)과 고농도 N+층(3)은 공통소오스로 작용한다.No. 3a to turn the low-concentration N to the P-type substrate 1, the lower-growing the layer 2 in the epitaxial growth method and, lightly doped N-layer (2) growing the high concentration N + layer 3 at the lower portion in the epitaxial growth method, As a sectional view of the state, the low concentration N − layer 2 and the high concentration N + layer 3 serve as a common source.
제3b도는 상기 P형 기판(1) 상부면의 예정된 부분에 LOCOS방식에 의해 필드산화막(4)을 형성한 상태의 단면도로서, 이 공정후에 노출된 P형 기판(1) 액티브영역의 표면에 자연산화막(5)이 성장된 것을 도시한다.3B is a cross-sectional view of the field oxide film 4 formed by the LOCOS method on a predetermined portion of the upper surface of the P-type substrate 1, and is naturally formed on the surface of the active region of the P-type substrate 1 exposed after this process. The oxide film 5 is grown.
제3c도는 트랜지스터의 문턱전압 조정을 위해 액티브영역의 P형 기판(1) 상부 내측에 고농도의 P형 불순물을 주입시켜 P+영역(6)을 형성한 상태의 단면도이다. 여기서 P+영역(6)의 농도는 P형 기판(1)의 농도보다는 높은 농도이나 N+보다는 훨씬 낮은 농도이다.3C is a cross-sectional view of a state in which a P + region 6 is formed by injecting a high concentration of P-type impurities into an upper portion of the P-type substrate 1 in the active region for adjusting the threshold voltage of the transistor. The concentration of the P + region 6 here is higher than that of the P-type substrate 1 or much lower than N + .
제3d도는 상기 공정후 P+영역(6) 상부면으로 고농도의 N+형 불순물을 주입시켜 드레인용 N+영역(7)을 P+영역(6)의 예정된 부분까지 형성한 다음, 베리드 산화막(8)을 상기 드레인용 N+영역(7) 상부에 예정된 두께로 성장시킨 상태의 단면도로서, 드레인용 N+영역(7)형성시 하부의 P+영역(6)이 P형 기판(1) 내부로 더 깊이 확산됨을 도시한다.FIG. 3d shows a high concentration of N + -type impurities are injected into the upper surface of the P + region 6 to form a drain N + region 7 to a predetermined portion of the P + region 6 after the process. (8) is a cross-sectional view of a state where the drain N + region 7 is grown to a predetermined thickness, wherein the lower P + region 6 forms the P-type substrate 1 when the drain N + region 7 is formed. It shows a deeper diffusion into the interior.
제3e도는 상기 베리드 산화막(8) 상부에서 트렌치 마스크를 이용하여 베리드 산화막(8), 드레인용 N+영역(7), P+영역(6), P형 기판(1), N-층(2)의 예정된 부분을 식각공정으로 제거하여 트렌치(9)를 형성한 상태의 단면도이다.FIG. 3E illustrates the buried oxide film 8, the drain N + region 7, the P + region 6, the P-type substrate 1, and the N − layer on the buried oxide film 8 using a trench mask. It is sectional drawing of the state which formed the trench 9 by removing the predetermined part of (2) by the etching process.
제3f도는 상기 트렌치(9) 표면에 게이트 산화막용 제 1 절연층(10)을 예정된 두께로 성장시키고, 제 1 절연층(10)과 베리드 산화막(Buride Oxide)(8), 필드산화막(4) 상부에 플로팅 게이트용 제 1 폴리실리콘층(11)을 예정된 두께로 증착한 상태의 단면도이다.FIG. 3f shows that the first insulating layer 10 for gate oxide film 10 is grown to a predetermined thickness on the surface of the trench 9, and the first insulating layer 10, the buried oxide film 8, and the field oxide film 4 are formed. A cross-sectional view of a state in which the first polysilicon layer 11 for floating gate is deposited to a predetermined thickness on the upper portion).
제3g도는 플로팅 게이트용 제 1 폴리실리콘층(11)의 예정된 부분 즉 베리드 산화막(8) 상부영역을 패턴공정으로 제거하여 플로팅 게이트(11A)를 형성한 다음, 플로팅 게이트(11A) 상부면에 내부폴리절연층용 제 2 절연층(12)을 예정된 두께로 성장시키고, 제 2 절연층(12), 버리드 산화막(8), 필드산화막(4) 상부에 제어게이트용 제 2 폴리실리콘층(13)을 증착한 상태의 단면도이다.FIG. 3g shows a predetermined portion of the first polysilicon layer 11 for floating gate, i.e., the upper region of the buried oxide film 8, by patterning to form the floating gate 11A, and then on the upper surface of the floating gate 11A. The second insulating layer 12 for the inner poly insulation layer is grown to a predetermined thickness, and the second polysilicon layer 13 for the control gate is disposed on the second insulating layer 12, the buried oxide film 8, and the field oxide film 4 above. ) Is a cross-sectional view of a state of being deposited.
제3h도는 상기 제 2 폴리실리콘층(13)의 예정된 영역을 패턴공정으로 제거하여 제어게이트(13A)를 형성한 상태의 단면도로서, 플로팅 게이트(11A)가 트렌치(9) 상부면의 드레인용 N+영역(7)에서 트렌치(9) 하부의 공통소오스용 N-층(2)까지 형성되어 있고, 플로팅 게이트(11A) 상부에 제어게이트(13A)가 적층되어 트렌치(9) 내부에 채워져 있음을 도시한다.FIG. 3h is a cross-sectional view of the control gate 13A formed by removing a predetermined region of the second polysilicon layer 13 by a pattern process, and the floating gate 11A has a drain N on the upper surface of the trench 9; It is formed from the region 7 to the N - layer 2 for the common source under the trench 9, and the control gate 13A is stacked on the floating gate 11A to fill the inside of the trench 9. Illustrated.
본 발명의 트렌치 내부에 플로팅 게이트 및 제어게이트가 적층되어 일반적인 플레쉬 EPROM셀 구조의 플로팅 게이트와 제어게이트와는 다른 구조를 가지며, 드레인은 기판내의 상부면에 형성된 N+영역이며, 이 N+영역이 연장되어 비트라인으로 사용되고, 소오스는 기판내의 하부면에 있는 N-층과 N+층을 이웃하는 셀과 공통연결시켜 사용하고, 기판의 트렌치 제어게이트 전압에 의해 수직방향의 채널이 기판의 트렌치 벽면을 따라 형성되어 단위셀 면적에 대한 셀 채널 폭의 비율이 높기 때문에 전류이동능력이 증대된다.Having a floating gate and the other structure and the control gate of the floating gate and the control gate are laminated typical flash EPROM cell structure in the trench of the present invention, the drain is an N + region formed in the top surface in the substrate, this N + region It is extended and used as a bit line, and the source is used by connecting N - layer and N + layer on the lower surface of the substrate in common with neighboring cells, and the vertical channel is formed by the trench control gate voltage of the substrate. Since the ratio of the cell channel width to the unit cell area is high, the current carrying capacity is increased.
또한, P형 기판 하부면에 에피택셜 성장(Epitaxial Growing)법으로 저농도 N-층과 고농도 N+층을 형성하고 P형 기판 상부면에 고농도 P+영역과 고농도 N+영역을 형성하고 P형 기판 보다 상대적으로 높은 농도의 P+영역으로서 트랜지스터에서의 채널문턱 전압을 결정하게 되는 요인이 되는데 본 발명의 트렌치형 EPROM셀에서 전기적으로 플레쉬 EPROM셀을 프로그램시킬 경우 드레인 접합에서의 높은 전기장(Electric Field)에 의해 핫캐리어(Hot Carrier) 발생이 용이하게 됨으로 인하여 프로그램 특성을 향상시킬 수 있다.In addition, a low concentration N − layer and a high concentration N + layer are formed on the lower surface of the P type substrate by using epitaxial growth, and a high concentration P + region and a high concentration N + region are formed on the upper surface of the P type substrate. The relatively high concentration of P + region is a factor that determines the channel threshold voltage in the transistor. When the electrically programmed EPROM cell is electrically programmed in the trench type EPROM cell of the present invention, a high electric field at the drain junction is present. By the hot carrier (Hot Carrier) can be easily generated, it is possible to improve the program characteristics.
또한 트렌치 구조로 EPROM셀을 형성함으로 제어게이트와 플로팅 게이트의 적층면적이 크기 때문에 종래의 셀 구조에 비교하여 상대적으로 높은 내부 폴리 절연체 중첩 캐패시턴스(Interpoly Insulator Overlap Capacitance) 값을 가지면서 플레쉬 EPROM의 캐패시터 결합비(Coupling Ratio) 개선에 의한 셀 특성을 향상시킬 수 있다.In addition, since the stacking area of the control gate and the floating gate is large because the EPROM cell is formed by the trench structure, the capacitor coupling of the flash EPROM has a relatively high interpoly insulator overlap capacitance compared to the conventional cell structure. It is possible to improve cell characteristics by improving the coupling ratio.
본 발명의 트렌치형 EPROM셀의 소거(Erase)동작은 공통소오스에서 높은 전압을 인가하여 소오스와 플로팅 게이트 사이의 전기장에 의한 포울러 노드헤임 터널링 메카니즘(Fowler-Nordheim Tunneling Mechanism)을 이용한다.The Erase operation of the trench type EPROM cell of the present invention utilizes a Fowler-Nordheim Tunneling Mechanism by an electric field between the source and the floating gate by applying a high voltage in a common source.
종래의 셀에서는 소거동작시 소오스의 높은 전압으로 인해 접합에서의 누설이 발생하면서 셀의 소거 특성이 저하되는 경우가 있지만 본 발명의 트렌치형 EPROM셀은 공통소오스의 접합(Junction)부분에 저농도의 N-층을 형성시킴으로써 접합 누설(Junction Leakage)을 방지할 수 있다.In the conventional cell, the erase characteristic of the cell may be reduced due to leakage at the junction due to the high voltage of the source during the erase operation. However, the trench type EPROM cell of the present invention has a low concentration of N at the junction of the common source. - it is possible to prevent junction leakage (junction leakage) by forming a layer.
상기한 바와 같이 본 발명에 의하면 종래의 플레쉬 EPROM과 비교할때 셀의 면적이 작아지고, 전류이동 능력, 프로그램 특성 및 소거특성을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, the area of the cell is reduced as compared with the conventional flash EPROM, and the current movement capability, the program characteristic, and the erase characteristic can be improved.
Claims (3)
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