KR940007296B1 - Comparator with improved output property - Google Patents

Abstract

The comparator circuit with an improved output characteristic comprises: a differential stage including a pair of first and second MOS transistors having a differential input structure, a third MOS transistor having the source connected to the sources of the first and second MOS transistors and having the gate connected to a bias voltage, first and second resistors respectively connected to the drains of the first and second MOS transistors, and a fourth MOS transistor having the gate and the drain respectively connected to the first and second resistors and having the source connected to a power voltage; and an output stage including fifth and sixth MOS transistors connected to receive an output of the differential stage, and a current mirror circuit connected between the drains of the fifth and sixth MOS transistors and a ground voltage, thereby performing a comparator operation at high speed.

Description

Comparator Circuit with Improved Output Characteristics

1 is a general comparator with hysteresis width.

2 is a conventional comparator circuit.

3 is another conventional comparator circuit.

4 is a comparator circuit having a large hysteresis width in accordance with the present invention.

5 is another comparator circuit having a large hysteresis width in accordance with the present invention.

The present invention relates to a comparator circuit having hysteresis characteristics among the interface circuits for converting an analog signal to a logic level. More particularly, the present invention relates to a comparator circuit having a large hysteresis width and stable operation at high speed regardless of process constant change and bias voltage change. It relates to a comparator circuit.

In general, in a comparator circuit including a differential stage and an output stage, a first input signal having a reference level and a second input signal having a level to be compared with a reference level are input to each of the pair of terminals, thereby providing a level of the second input signal. The output signal having the logic level determined by is output from the differential output terminal. In addition, the output signal of the differential stage is supplied to the output stage, and the output signal of the differential stage therethrough is inverted and amplified.

In this conventional comparator circuit, if the level of the second input signal is greater than the level of the first input signal and the voltage level difference between the two input signals increases, the first input signal of the differential stage is supplied to the gate. The transistor approaches a blocking state. Therefore, the output voltage level of the differential stage gradually rises, and the output stage transistor (P channel type) to which the output signal of the differential stage is supplied to the gate is cut off.

After such a blocking state of the transistor is generated, it is necessary to turn on the transistors in the blocking state if the level of the second input signal drops and becomes lower than the first input level. However, since the drift capacitance is usually present in the semiconductor device, a long time is required to conduct the transistor due to the time for charging the drift capacitance. Therefore, there arises a problem that the operating speed of the comparator circuit is remarkably delayed, especially when the level of the second input signal falls from the high level to the low level.

A comparator with hysteresis characteristics is called a Schmitt circuit. The purpose of this circuit is to remove noise and make high input signal into logic level square wave when noise occurs in input signal.

A large hysteresis width is necessary to remove the noise when the noise is larger than the input signal. Of course, the same effect can be obtained by making the input signal and the noise level small through the attenuator and then outputting the input signal through the comparator with a small hysteresis width. When unnecessary noise such as power supply noise is increased through external components, a comparator having a large hysteresis width is required.

To understand the background of the present invention, a conventional comparator circuit having a differential stage and an output stage will be described according to FIGS. 1 and 2.

1 is a comparator having a conventional hysteresis characteristic, which is composed of a comparator COMP, a resistor R _f1 , R _f2 and a reference voltage source Vref. A circuit diagram of the comparator COMP is shown in FIG.

As shown in Figure 2, the comparator consists of a differential amplifier and an inverted amplifier circuit, which are described in detail in pages 327-349 of Allen and Holberg's "CMOS Analog Circuit Design" (HOLT, RINEHART AND WINSTO). You can see it in the book.

In the circuit shown in FIG. 2, the output resistance of the differential amplifier circuit driving the input transistor M11 of the inverted amplifier circuit is determined by the active resistances of the MOS transistors M10 and M2, and thus works together with the capacitor C _L '. As a result, the input voltage of the inverted amplifier circuit changes slowly, and thus the comparator circuit does not operate at high speed.

In addition, since the MOS transistor M11 is changed from the 'off' state to the 'on' state, the capacitor C _L acts on the output, thereby slowing the comparator output. Therefore, another comparator circuit of high speed operation has been proposed.

Another conventional comparator circuit shown in FIG. 3 proposed in accordance with the above requirement works with capacitors C _L1 and C _L2 by replacing the MOS transistors M9 and M10 in FIG. 2 with passive resistors R1 and R2. It consists of a circuit that reduces the output resistance and connects the inverted amplifier circuits to the differential amplifier circuits of the MOS transistors M4 and M5 and the outputs to the MOS transistors M6 and M7, which perform a current mirror operation.

In addition, if the resistor R3 is connected in series with the resistors R1 and R2 and an appropriate value is selected, the MOS transistors M4, M5, M6, and M7 constituting the inverted amplifier circuit are always in the 'on' state. Comparator output characteristics are faster.

However, a comparator circuit requiring a large hysteresis width in spite of the high speed operation has the following problems.

If the hysteresis width required is greater than the designed input dynamic range, that is, if the comparator non-inverting input voltage (Vp) is lower than the sum of the 'turn-on' voltages of the transistors (M2, M3), then the MOS transistor (M3) ) Is in a 'linear' state so that the current flowing through the MOS transistors M1 and M2 to the resistors R1 and R2 becomes small.

If the current is too small and flows to either side of the MOS transistors M1 and M2, if the voltage applied to the resistors R1 and R3 or R2 and R3 is lower than the threshold voltages of the MOS transistors M4 and M5, The comparator circuit shown in FIG. 3 does not operate normally. Also, even when the bias voltage V _B changes, the comparator circuit does not operate normally.

In more detail, the process constants representing electrical characteristics parameters such as resistance value, capacitor value, MOS transistor threshold voltage, current gain of bipolar transistor, etc. for realizing integrated circuit in semiconductor manufacturing process are changed or When the voltage changes, the output terminal does not operate at all when the gate voltage of the MOS transistors M4 and M5 constituting the output terminal is smaller than the threshold voltages of the MOS transistors M4 and M5. When the voltage V _N is higher than the voltage V _P and the current supplied from the MOS transistor M3 flows through the MOS transistor M1, the voltage V _DD is between the gate of the MOS transistor M4. The applied voltage V _X1 and the current I ₁ flowing in the resistor R1 are as follows.

Where μ is the mobility of electrons, the gate capacitor value of the Cox MOS transistor, W ₃ is the gate width of the MOS transistor M3, L ₃ is the gate length of the MOS transistor M3, and V _THN is the threshold voltage of the N MOS transistor. Indicates.

At this time, when Cox is smaller than the process center value and the threshold voltage of the N MOS transistor is increased due to the change of the process constant, the voltage V _X1 is designed when the current I ₁ decreases and the resistances R1 and R3 decrease. It is smaller than the center value.

If the threshold voltage V _THP of the P MOS transistor is increased and the voltage V _X1 is smaller than the threshold voltage V _THP , the output terminal including the MOS transistors M4, M5, M6, and M7 may not operate.

In addition, when the bias voltage V _B is used to hold an internal bias using the power supply voltage, when the power supply voltage is lowered, the current I ₁ may be smaller, which may cause the same disadvantage.

Therefore, the circuit shown in FIG. 3 is difficult to operate stably in terms of change of process constant and change of power supply voltage. On the other hand, by designing a large current (I ₁ ) and resistors (R1, R3) can always make the low voltage (V _X ) greater than the P MOS transistor threshold voltage (V _THP ), but in this case a large hysteresis width is limited . That is, to obtain a large hysteresis width, the voltage V _P must be increased. When the gate-drain voltage V _{GD of the} MOS transistor M2 is greater than the threshold voltage V _TH N, the MOS transistors M2 and M3 are linear. Operation in the area slows down and the hysteresis widths deviate from the design values and affect process constant changes. The condition that the MOS transistor M2 operates in the saturation region is

And, as the voltage V _X1 increases, there is a constraint that the voltage V _P must be made smaller.

Accordingly, an object of the present invention is to provide a comparator circuit which operates stably at high speed even if a hysteresis width deviates from the input dynamic range due to a change in process constant or a design error in a comparator requiring a large hysteresis width.

A comparator circuit for achieving the object of the present invention is a pair of first and second MOS transistors having a differential input structure with the input input voltage and the reference voltage as inputs, and the source of the first and second MOS transistors. A third transistor to which a drain is connected and a bias voltage is applied to a gate terminal, a pair of first and second resistors connected to drains of the first and second MOS transistors, and between the first and second resistors and a power source A pair of fifth and sixth MOS transistors having a differential stage configured with a third resistor inserted into the pair and an output of the differential stage, and a current mirror circuit inserted between each drain and ground of the fifth and sixth MOS transistors. A comparator circuit having a configured output stage, wherein the comparator circuit obtains a comparative output from a connection point of the sixth MOS transistor and the current mirror circuit, wherein the first and second low ends are replaced with the third resistor. Whose gate and drain respectively connected to and is characterized in that the fourth MOS transistor power is applied to the source replacement.

Hereinafter, more details of the present invention will be described with reference to the accompanying drawings.

4 is a comparator circuit diagram of the present invention, wherein the first and second transistors M1 and M2 having a differential input structure having a comparison target input voltage V _N and a reference voltage V _P as inputs, and the first and second transistors. A third MOS transistor M3 having a drain connected to a source of the second MOS transistor M1 and M2 and a bias voltage V _B applied to a gate terminal, and the first and second MOS transistors M1 and M2. A fourth MOS transistor having its gate and drain connected to the first and second resistors R1 and R2 and the first and second resistors R1 and R2 respectively connected to the drains of the transistors) and supplying power to the source. A differential terminal consisting of (M0) and the fifth and sixth MOS transistors M4 and M5 to which the output of the differential terminal is input, and inserted between the respective drains and grounds of the fifth and sixth MOS transistors M4 and M5, respectively. It consists of an output stage consisting of current mirror circuits M6 and M7.

In the present invention, the conventional resistor R3 is replaced with the P MOS transistor M0. According to the P MOS transistor M0, the MOS transistors M4 and M5 are always in a 'turn on' state regardless of the current supplied by the MOS transistor M3 and the threshold voltages of the MOS transistors M4 and M5. In addition, even if the threshold voltages of the MOS transistors M4 and M5 change, the voltage applied to the gates of the MOS transistors M4 and M5 changes accordingly, so that stable operation is performed regardless of the process constants of the MOS transistors M4 and M5. .

In other words, the voltage V _X2 applied between the power supply voltage V _DD and the gate of the MOS transistor M4 is expressed as follows.

Here, W _{0 represents} the gate width of the P MOS transistor M0, L _{0 represents} the gate length of the P MOS transistor M0, V _THP represents the threshold voltage of the P MOS transistor, and the current I ₁ is represented by equation (II). Is expressed in the same way as

Thus, V _{X2 THP} .

As can be seen from the above equation (IV), the voltage V _X2 is always higher than the threshold voltage V _THP of the P MOS transistor regardless of the change of the power supply suppression V _DD and the change of the process constant. In operation, a large hysteresis can be obtained by increasing the reference voltage (V _P ).

The remaining symbols are the same as in FIG.

FIG. 5 is a circuit diagram of a modification of the present invention in which the relationship with FIG. 4 is formed using the complementary relationship between the PMOS and the NMOS.

In the present invention, the MOS transistor M6.M7 constituting the output stage, that is, the current mirror may use a Wilson current mirror or a cascode current mirror to increase amplification gain.

According to the circuit of the present invention, the comparator operation can be performed at high speed and hysteresis is performed even when the designed bias voltage is changed even when the resistance value is changed, the process constant such as the threshold voltage of the MOS transistor or the designed bias voltage are changed under the condition that a large hysteresis width is required. Even when the width is out of the input dynamic range, the comparison operation can be performed stably.

Claims (2)

A pair of first and second MOS transistors M1 and M2 having a differential input structure in which a comparison target input voltage V _N and a reference voltage V _P are input, and the first and second MOS transistors M1. And a drain thereof are connected to a source of M2 and are respectively connected to drains of the third and second MOS transistors M1 and M2 to which a bias voltage V _B is applied to a gate terminal. A differential stage comprising a pair of first and second resistors R1 and R2, a third resistor R3 inserted between the first and second resistors R1 and R2 and a power supply voltage V _DD , and A current mirror circuit M6 inserted between each drain and ground of the pair of fifth and sixth MOS transistors M4 and M5 to which the output of the differential stage is input, and the fifth and sixth MOS transistors M4 and M5. And a comparator circuit having an output stage consisting of M7) and obtaining a comparison output from a connection point of the sixth MOS transistor and the current mirror circuit. (R3) a comparator circuit, characterized by said first and second resistors (R1, R2) is respectively connected to its gate and drain and is replaced by a fourth MOS transistor (M0) power is applied to the source and configured. The method of claim 1, wherein the first, second and third morph transistors (M1, M2, M3) are of the N-channel type, the fifth and sixth MOS transistors (M4, M5) are P-channel type, or Comparator circuit, characterized in that the reverse.