KR940007155B1 - Plague oscillator for synchronization - Google Patents

Abstract

The synchronous flag generating device of a pointer in a synchronous multiplexer includes a state detecting circuit for generating a stable or unstable state signal, a state converting circuit for generating a state converting signal, a flag bit generating circuit for generating a flag bit alarm signal, and an alarm transmitting circuit for transmitting a stable arrival signal to an external central processing unit in response to the stable state signal and transmitting an alarm signal to the central processing unit in response to the unstable state signal, thereby minimizing an influence caused by a temporary unstable state of a circuit.

Description

Synchronous Flag Generator

1 is a flag configuration diagram.

2 is a timing diagram of a signal processed in the present invention.

3 is a detailed circuit diagram showing an embodiment of the present invention.

4 is a flow diagram in accordance with the operation of the present invention.

* Explanation of symbols for main parts of the drawings

100: state detection unit 200: state conversion unit

300: flag bit output unit 400: alarm transmission unit

101: shift unit 102: logical sum unit

103: state detection signal output unit 201: state conversion data output unit

202: set signal output section A1, A2, A5 to A10, A12: AND gate

A3, A4, A11: NAND gate OR1 to OR5: Ora gate

D1 to D18: D flip flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization flag generating apparatus, and a synchronization flag generating apparatus of a pointer synchronization type for transmitting a synchronization signal in a synchronization transmission system.

In general, a pointer synchronization method is used to multiplex and transmit sub-signal data in a main frame of a synchronization signal. The pointer indicates the position of the sub-signal frame within the main frame and performs the function of frequency adjustment. The pointer consists of a flag and a pointer value. The pointer informs you of a change in the pointer value. Therefore, when the sub-signal data is newly started or when there is a need for re-delivery, a flag must be set and sent to the counterpart transmission apparatus.

Accordingly, the present invention provides a synchronization flag generator capable of forcibly generating a flag bit that can be used for the synchronization pointer at the initial power-on and, if necessary, by control. The purpose is to do that.

According to an aspect of the present invention, there is provided a synchronous flag generator of a pointer in a synchronous multiplexer, wherein a reset signal, an external stable signal, a pointer value stable signal, and a forced control signal are input and output a status signal. A timing clock for receiving a state signal from the state detecting means and receiving a state signal from the state detecting means, the state converting means operating according to an output signal of the state detecting means and an external set control signal. And an alarm generating means for reporting as a warning to the CPU when the state signal transitions from the status detecting means, and releasing the alarm when the CPU responds.

Hereinafter, the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a frag bit configuration.

As shown in the figure, the flag consists of 4 bits and has 1001 data in the set, 0110 data in the normal state, and 1111 data in the alarm state (AIS). In particular, set data must be sent only once per -frame period.

2 is a timing diagram of signals processed in the present invention, and FIG. 3 is a detailed circuit diagram showing an embodiment of the present invention.

In the drawing, 100 is a state detection unit, 200 is a state conversion unit, 300 is a flag bit output unit, 400 is an alarm transmission unit, 101 is a shift unit, 102 is a logical sum unit, 103 is a state detection signal output unit, and 201 is state conversion data. The output section 202 represents a set signal output section, A1, A2, A5 through A10 and A12 represent an AND gate, A3, A4 and A11 represent a NAND gate, OR1 through OR5 represent an OR gate, and D1 through D18 represent a D flip flop.

The state detection unit 100 receives an reset signal, an external circuit stabilization signal, a pointer value stabilization signal, and a forced control signal (1, 2, 3, 4 signals in FIG. 2) from the outside shown in FIG. A shift unit 101 connected to the gate A1 and the output terminal of the AND gate A1 and having a plurality of D flip-flops D1 to D6 connected in series to shift the output of the AND gate A1; A logic sum unit 102 for ORing each of the outputs of the plurality of D flip-flops D1 to D6 constituting the shift unit 101 by three signals, and the output of the logic sum unit 102 after receiving the output of the logic sum unit 102. An AND gate A2 and a state detection signal output unit 103 for receiving an output signal of the AND gate A2 and outputting a state signal indicating stability and instability of the circuit.

The state detection unit 100 receives the signal information (1, 2, 3) and the control signal (4) for the stable state from the external circuit at the time of initialization (reset), and receives appropriate conditions (i.e. The state signal 17 is outputted by determining that the circuit has reached a stable state by applying the steady state holding signal for a time), and the state signal 17 is provided to the state conversion unit 200.

In addition, after reaching the stable state (that is, after the state signal is output), if it is unstable due to any reason such as external factors determined from the signals 2, 3, 4, etc. If it is determined that 16 is '0', it is indicated as the instability signal 18, and the instability signal 18 is supplied to the alarm transmitter 400.

Looking at the more detailed operation of the state detection unit 100 as follows.

When the reset signal 1, the external circuit stabilization signal 2, the pointer value stabilization signal 3, and the forced control signal 4 are input, all of the four signals are in the '1' state. The output 5 becomes '1'. The output signal of the AND gate A1 is input to a shift unit 101 connected to the rear stage, and the input signal is sequentially ordered to a plurality of D flip-flops D1 to D6 triggered by an external clock signal 19. Is shifted to.

In the present invention, the shift unit 101, as a preferred embodiment, consists of six D flip flops D1 to D6 connected in series, and the first to third D flip flops D1 to D3 of the D flip flops. The outputs 5, 6, and 7 are input to the OR gate OR1 in the logic matching section 102, and if any one is '1', the output signal 12 is output as '1', and the second to fourth D flip-flops are output. The outputs 6, 7, and 8 of D2 to D4 are input to the OR gate OR2 in the logic summation 102, and if either one is '1', the output signal 13 becomes '1'. Similarly, the third to fifth and fourth to fourth D flip-flop outputs 7,8,9 and 8,9,10 are respectively input to OR gate OR3 and OR1, so that one is '1'. ', Output signal 14 and output signal 15 becomes' 1'.

The output signals 12, 13, 14, and 15 of the OR gates 12 to 15 are output as '1' when the signals are all '1' by the AND gate A2.

Therefore, if the output of the AND gate A2 is to be '1', the state in which all four input signals 1, 2, 3, and 4 are '1' is maintained four times with respect to the clock 19. That is, at the initial power-on, the circuit is output as the state detection signal 16 indicating the stable state only after a time (about 500 mu s) at which sufficient stability is ensured.

In addition, even when the input signal (l, 2, 3, 4) drops to '0' due to a temporary instability while the circuit is in operation, the output signals 12, 13, 14, and 15 of the logic sum 102 are simultaneously '0'. If it is not a condition, the AND gate A2 output signal 16 continues to be output as a signal indicating a stable state as a '1' state. In other words, the status output 16 does not become '0' unless it becomes '0' three times in succession.

The state output signal 16 enters the inputs of the D flip-flops D7 and D8 in the state detection signal output unit 103 and is shaped by the clock 20 from the outside to form the final signal 17 of the state detection unit 100. , 18). D flip-flop (D7) is when the initial reset signal (1) is '0', the final signal 17 is '0', D flip-flop (D8) is the initial reset signal (1) is '0' , The final signal 18 becomes '1'. In the normal operation, the output signal 17 of the D flip-flop D7 and the inverted output signal 18 of the D flip-flop D8 have an inverse relationship.

Next, the state conversion unit 200 includes a state conversion data output unit 201 including two D flip flops D10 and D1 and a NAND gate A3, and three D flip flops IX and D12. A set signal output unit 202 including a D13, a NAND gate A4, and an AND gate A5, A6, an output of the state conversion data output unit 201, and an output of the set signal output unit 202; An AND gate A7 for logical ANDing is provided.

In the state conversion unit 200 configured as described above, the stable state signal 17 and the external control signal 21 received from the state detection unit are adapted to the appropriate periodic conditions (125 μS) by the external timing signals 21, 22, and 23. The state conversion signal 34 is outputted to the later flag bit output unit 300. That is, the state conversion unit 200 transmits the signal 17 detected by the state detection unit 100 to the clocks 22 and 23. To set or reset (normal) state.

More specifically, the operation of the state conversion unit 200, the stable state signal l7 detected by the state detection unit 100 is latched by the external clock 23 in the D flip-flop D10 and the latched signal ( 24 is again latched by outer clock 22 at D flip-flop D1. The inverted clock 25 and the previous latch output 24 of the D flip-flop D1 are NAND logic processed at the NAND gate A3 to be output 26 as state transition data. As shown in FIG. 2, it can be seen that when the detected signal 17 is '1', the output 26 of the NAND gate A3 is in the 'low' state once. In his case, it remains 'high'. In this way, when the initial power-on circuit is stabilized and the pointer value is determined to be valid, it is converted to maintain the set state at once.

In addition, when the circuit is operating normally, in order to generate a set signal arbitrarily, the output signal 17 of the D flip-flop D7 is received by the external control signal 21, and the D in the set signal output unit 202 is received. Once latched on the flip-flop D9, the latched signal 27 is input from the D flip-flop D12 to the external club 23, and the latched signal 28 is input on the D flip-flop D13. The latch is latched to the external clock 22 to obtain the inversion signal 29. When the signal 29 and the previous latch signal 28 are negatively multiplied by the NAND gate A4, the conversion signal 30 can be obtained. On the other hand, the inverted output 31 of the D flip-flop D12 is returned. Along with the set signal 1, the AND gate A5 is applied to the clear terminal of the D flip-flop D9 (32), and the output signal 27 and the reset signal 1 of the D flip-flop D9 are reset. And the output signal 26 of the NAND gate A3 are input to another AND gate A6 and are negatively multiplied so as to be applied to the clear terminal of the D flip-flop D13 (33).

When the output signal 32 of the AND gate A5 is '0', the D flip-flop D9 is cleared and the output 27 returns to the '0' state. Accordingly, when the external set control signal 21 becomes '1' from '0' state, the set signal is issued once and then returns to normal.

On the other hand, the conversion signals 26 and 30 are AND-processed by the AND gate A7 to form an output signal 34. The final state conversion output 34 thus obtained is a flag bit output unit ( 300).

The flag bit output unit 300 receives the output 34 of the state conversion unit 200 and outputs the output signal 34 by the external clock 38 at a desired timing, when the output signal 34 of the state conversion unit 200 is generated. The conversion signals 50 and 51 are output by converting one of the branch-type flag signals (flag set, flag normal, flag AIS).

Looking at the specific operation, the output signal 34 of the state conversion unit 200 is latched by the external clock 38 in the D flip-flop (D14) to obtain the inverted output 50, and similarly the D flip-flop (D15) Is inputted to the external clock 38 to obtain an output 51 and an inverted output 52. Here, the output signal 50 of the D flip flop D14 is output with N1 and N4 bits, and the output signal 51 of the D flip flop D15 is output with N2 and N3 bits. The output signal 50 of the D flip flop D14 and the inverting output 52 of the D flip flop D15 are subjected to an AND process by the AND gate A10 to obtain a set state output 40.

However, as long as the state stabilization signal 17 is kept at '0' at the initial time, the flag bits need to be kept in an alarm state. A function for forcibly setting the flag bits is also required. To this end, an AND gate A8 and an AND gate A9 are used. That is, when the state stabilization signal 17 is maintained at '0', the AND gate A8 connected to the reset terminal of the D flip-flop D14 receives the state stabilization signal 17 as one input. The output signal 35 is output as '0' to clear the D flip-flop D14 to make the N1 and N4 bits '1', and receive the state stabilization signal 17 as one input and the D flip-flop D15. The output 36 of the AND gate A9 having the output terminal connected to the set terminal of N) sets the D flip-flop D15 to bring the N2 and N3 bits into a 'q' state.

Then, when '0' is applied to the signal 37, since the input signal is applied to the other input terminal of the AND gate A9 and the set terminal of the D flip-flop D14, the flag bit is reset in the circuit. Applying '0' to the signal 39 is applied to the other input terminal of the AND gate A8 and the set terminal of the D flip-flop D15, so that the flag bit is in the set state 1001 on the circuit.

When the alarm transmission unit 400 generates the stable state signal 17 from the state converting unit 100, the alarm transmission unit 400 reports the stable state signal 17 to the CPU, which is an external control device, and generates an alarm when the instability signal 18 occurs. The signal is reported to the external CPU as a signal 49, and the state is automatically cleared when the external CPU accesses it.

In more detail, the alarm transmitter 400 emits an alarm signal 49 when the steady state output signal 17 of the state detector 100 transitions from '0' to '1' and sends it to the CPU. When the unstable state output signal 18 of the detector 100 transitions from '0' to '1', the alarm signal 49 is also issued and sent to the external CPU. After receiving the alarm, the CPU determines the state and returns the alarm generator 400 to the normal state through the read signal 41.

D flip-flop D17 at the point where the steady state detection signal 17 transitions from '0' to '1' in the state detection unit 100 at the initial power-on. The input signal 45 of the D flip-flop D7 is output as the output signal 47 when applied to the clock terminal of. When the state detection unit 100 falls into an unstable state, the instability detection signal 18 is applied to the clock terminal of the D flip-flop D18 at the point where the instability detection signal 18 transitions from '0' to '1'. The input signal 45 of the flop D18 is output as the output signal 48. When one of the two signals 47 and 48 becomes '1', the alarm signal 49 is issued by the OR gate OR5. This signal 49 is immediately transmitted to the CPU and simultaneously to the input of the NAND gate A11. As long as the recognition signals 41 and 42 of the CPU do not become '1', the alarm signal 49 continues to be in the '1' state, and the NAND gate at the moment when the recognition signals 41 and 42 of the CPU becomes 'l'. The output 44 of (A11) becomes '0', thereby the AND gate A12 output signal 45 which receives the output signal of the NAND gate A11 and the external reset signal 1, and the The output signal 46 of the D flip-flop Dl6, which receives the output of the AND gate A12, also becomes '0', so that the D flip-flop D17 having a clear terminal connected to the output terminal of the D flip-flop D16. ) And D flip flop (D18) are cleared. Therefore, the alarm output 49 returns to '0' to release the alarm state.

At this time, the output signal 46 applied to the clear terminal is delayed by another external clock 43 to be applied to the clear terminal so as not to be simultaneously applied to the terminal and the clear terminal.

4 is a flow chart briefly illustrating the operation of the present invention as described above.

FIG. 4 is a flow chart briefly showing the operating state of the present invention as described with reference to FIG. 3, which determines a stable state at initialization (power on), and inserts a flag AIS when the stable state is not reached. When the steady state is reached, the flag is reported to the CPU and the flag is set at the same time. This flag bit is latched and held, and continues to be monitored. When monitoring the instability and transitioning from the stable state to the unstable state, the alarm signal is sent to the CPU and the flag AIS is inserted at the same time to continuously monitor the stable state. In the stable state, it is called a flag set when the set control signal is allowed or not. If it is not present, the flag is set to normal and held by the flag bit latch.

The present invention, which can be configured and operated as described above, can forcibly generate a flag bit that can be used for a synchronization pointer at the initial power-on and, if necessary, by control. In addition, since the frag bit must maintain high reliability, there is an effect that the effect can be minimized from the transient stability of the circuit.

Claims (9)

A synchronous flag generator of a pointer in a synchronous multiplier, comprising: signal information (1, 1) about a stable state consisting of a reset signal, an external stable signal, and a pointer value stable signal input from the outside at initialization (reset); 2, 3) and the state detecting means 100 for outputting a stable state signal when the forced control signal, which is a control signal, remains stable for a predetermined time, and outputs an unstable state signal when the input signals display an unstable state for a predetermined time or more. And a stable state signal from the state detecting means 100 and a control signal from the outside are output as a state change signal converted into a set and reset (normal) state according to a predetermined condition period by an external timing signal. The state conversion means 200 and the state conversion signal output from the state conversion means 200 by receiving an external clock of the form of a flag signal (flag set, Frag Converts to one of the phase AIS and outputs the converted signals 50 and 51, receives the stable state signal 17 from the state detection means 100, and sets and outputs the flag bits directly. The flag bit output means 300 for outputting the lag bit alarm signal and the stable state signal from the state converting means 200 are provided to the external CPU as the stability reaching signal, and the alarm is received if the unstable state signal is input. And an alarm transmission means (400) which is provided as a signal to the external CPU and is automatically cleared upon access of the external CPU. The method of claim 1, wherein the state detecting means (100) comprises: first logical multiplication means (A1) for inputting a reset signal, an external stability signal, a pointer value stability signal, and a forced control signal, and first to sixth flip-flops ( Shift means (011) for connecting D1 to D6 in series and shifting the output of the first logical multiplication means (A1), first to fourth OR gates (OR1 to OR4) are connected in parallel, and the shift means Logical sum means 102 for logically summing each shifted output of 101 by three signals, second logical multiplication means A2 for ANDing the output signal of the logical sum means 102, and the second logical multiplication means ( And a state detection signal output means (103) for latching the output signal of A2) to output a state detection signal. 3. The OR circuit according to claim 2, wherein the logical sum means (102) is a thirteenth input OR gate (ORl), the second, third, A twenty-third input OR gate OR2 for inputting the outputs of the 4D flip-flops D2, D3 and D4, and a thirty-third input for the outputs of the third, fourth and fifth D-flop flops D3, D4 and D5. And an OR gate OR3 and a 43rd input OR gate OR4 for inputting the outputs of the fourth, fifth and sixD flip-flops D4, D5 and D6. . 4. The state detection signal output means (103) according to claim 3, characterized in that it comprises seventh and eighth D flip-flops (D7, D8) having data inputs connected to the second logical product (A2), respectively. Synchronous flag generator. The apparatus of claim 1, wherein the state conversion means 200 outputs state conversion data valid for one frame period only when the state signal detected by the state detection means 100 transitions to a stable state. 201) of the set signal output means 202, the state conversion data output means 201 and the set signal output means 202 for outputting set data valid only once for a frame period according to an external set control signal in normal operation. And a seventh logical multiplication means (A7) for logical multiplication of the outputs. The state conversion data output means 201 is configured to output a state detection output signal of the seventh D flip-flop D7 generated after the state is stabilized for a predetermined time at initial power-on. The latch output of the 10D flip-flop Dl0 to latch, the first 1D flip-flop Dl1 and the 10D flip-flop D10 latching the output signal of the 10D flip-flop D10 and the 11D flip-flop D10. And a first negative logic unit (A3) for inputting the inverted output of D11). The set signal output means 202 is configured to input an external set control signal and a state detection signal of the 7D flip-flop D7 when an arbitrary set signal is generated when the circuit is normally operating. The inverted signal output and reset signal of the ninth D flip flop D9 for latching, the twelfth D flip flop D12 for latching the output signal of the ninth D flip flop D9, and the twelfth D flip flop D12 A fifth logical multiplication means A5 for multiplying and applying to the clear signal terminal of the ninth D flip flop D9, a thirteenth D flip flop D13, and the twelfth D latching an output signal of the twelfth D flip flop D12; Output signals and reset signals of the second negative logic means A4 and the ninth D flip-flop D9, which take the non-inverted output of the flip-flop D12 and the inverted output of the 13D flip-flop D13 as input. And logically multiplying the output signal of the first negative logical multiplication means (A3) as an input. And a sixth logical product means (A6) for outputting to the clear terminal of the flip plane (D13). The 14th and 15D flip-flops D14 and D15 and the 14D flip-flop D14 for inputting and latching the output of the state converting means 200. A tenth logical means (A10) for outputting a set state signal by ANDing the inverted output of the fifteenth flip-flop (D15) and the eighth logical means for setting the fourteenth flip-flop (D14) A8) and a ninth logical product means (A19) for setting the fifteenth flip-flop (D15). The method of claim 1, wherein the alarm generating means (400) is configured to logic the output of the third negative logic means (A11), the third negative logic means (A11) and the reset signal to which the alarm signal and the recognition signal is input. The non-inverted output signal of the twelfth logical multiplication means A12, the 16th flip-flop D16 and the seventh D flip-flop D7 for latching the output signal of the first and second logical supply means A12 are clock terminals. 17D flip-flop Dl7 and 8D flip-flop, which are applied to the output signal of the twelfth logical means A12, are inputted to the data input terminal and are cleared by the output signal of the sixteenth D flip-flop D16. An inverted output signal of (D8) is applied to the clock terminal and is input to the output signal data input terminal of the twelfth logical unit A12, and is cleared by the output signal of the sixteenth flip-flop D16. (D8), the non-inverted output signal of the 17th D flip-flop (D17) and the non-inverted output signal of the 18th D flip-flop (D18) is logic The fifth loop lag generator for synchronization, characterized in that it comprises a logical OR means (OR5) for outputting an alarm signal.