KR940006925B1 - Current source having controllable temperature coefficient - Google Patents

Abstract

In a circuit arrangement for providing a current having a controllable temperature coefficient of current, a diffused resistor (334) is used to set up a reference current in a current source (40) which has a temperature coefficient dependent upon the diffused resistor. A current mirror (352, 354, 356) receives the reference current and passes a portion of it through an ion implanted resistor (360). The output current has a temperature coefficient which is a function of the original temperature coefficient of current and a nonzero algebraic multiple of the temperature coefficient of the implanted resistor. By appropriate selection of the resistor values and types, the temperature coefficient of the output current can be set to any desired value.

Description

[Name of invention]

Current source with adjustable temperature coefficient

[Brief Description of Drawings]

1 is a block diagram showing a quadrature demodulator without an inductor of the present invention.

2 is a graph showing the phase shift characteristics of the phase shift network and the active filter of the present invention.

3 is a timing diagram showing various signals of the present invention.

4 is a schematic illustration of the active filter of the present invention in accordance with the associated circuitry.

5 is a schematic diagram detailing the active filter, phase shift network, and frequency trim network of the present invention.

6 is a schematic diagram detailing the current source and temperature compensation network of the present invention.

7 is a schematic diagram detailing the exclusive OR and low pass filters of the present invention.

Detailed description of the invention

[Background of invention]

[One. FIELD OF THE INVENTION

The present invention relates generally to field current sources, and more particularly, to the current source having controllable temperature characteristics used in integrated circuits.

[2. background]

With the trend toward miniaturizing FM transmitters and receivers, FM demodulators have become one of the most difficult circuits to miniaturize. This is mainly due to the appropriate high frequencies normally involved, and due to the inability to reduce the size of the inductor with suitable high inductances and Q coefficients used in such demodulators. In reducing the size of such devices, it is also important that the FM demodulator can be operated at very low voltage and current levels, since the size of the battery is a fundamental obstacle to miniaturizing such devices.

Some types of FM gradient detectors and the like also use crystal or ceramic resonators as demodulation circuitry. This has the disadvantage of using inductors due to the brittleness, size and cost of such devices.

Inductors used in quadrature demoodulators are one of the most expensive, heavy and most unreliable components used in small receivers such as paging receivers. Therefore, it is desirable to exclude the use of such components in small devices as well as in large electronic devices.

Some demodulators can be implemented without the use of an inductor, such as phase locked loops and pulse counting demodulators. Unfortunately, these demodulations have many drawbacks that cannot operate at the very low voltage and current levels required for battery operated receivers such as paging receivers. The demodulator is also a low Q device exhibiting low noise performance. Apart from operating at frequencies below approximately 200 KHz, pulse count demodulators have another drawback of providing very low amplitude reconstruction signals. Therefore, it is desirable to provide a quadrature demodulator that can be sufficiently realized in the form of integrated circuits and that can be operated at low voltage and current levels. Quadrature demodulators are frequently used in FM communication applications due to desirable characteristics such as high voice output and high signal-to-noise ratio. Therefore, it is highly desirable to provide an inductorless vision quadrature demodulator that can be fully integrated on a single integrated circuit.

Unfortunately, there are many technical challenges that must be overcome in integrating quadrature demodulators, which are optimally implemented, especially when demodulators must operate stably over a wide range of temperatures and under all ambient conditions and variations of integrated circuit processes. There is an urgent need to take steps to ensure the demommability of the demodulator. Under these conditions, high temperature stability circuits are required, and it is very important to be able to precisely control temperature coefficients independent of the temperature coefficients of each component. It is also important to have the ability to initially tune or adjust the circuit to eliminate manufacturing variations in component values. The present invention provides a solution to the above and other problems.

[Summary of invention]

It is an object of the present invention to provide an improved quadrature demodulator.

Another object of the present invention is to provide a quadrature demodulator without an inductor.

Another object of the present invention is to provide a trimmable temperature stable mutual conductance amplifier for use as an active filter in a quadrature demodulator.

Another object of the present invention is to provide a demodulator that operates at low voltage and current levels to facilitate operation and miniaturization on battery cells.

Another object of the present invention is to provide a temperature stable current source for use in an integrated circuit such as the present demodulator.

Another object of the present invention is to provide a method for trimming a coilless FM demodulator.

It is a further object of the present invention to provide an integrated quadrature demodulator that operates under very low voltage and current conditions.

It is yet another object of the present invention to provide an integrated quadrature demodulator that can be trimmed or adjusted in frequency while the final integrated circuit is still in wafer form.

The above and other objects, advantages and features of the present invention will become apparent to those skilled in the art through the following description of the present invention.

In one embodiment of the invention, a circuit arrangement for providing a current having a controlled temperature coefficient of current comprises an input node for receiving a first current, the first current being a first predetermined temperature coefficient of current. Have A reference resistor having a predetermined reference temperature coefficient of resistance receives the first current and generates a temperature dependent signal. The current multiplication mirror circuit provides, in response to the temperature dependent signal, a second temperature coefficient of current that depends on the first predetermined temperature coefficient of current and a second current having a nonzero logarithm of the predetermined reference temperature coefficient of resistance. .

While the features of the invention are set forth in the appended claims, with reference to the accompanying drawings, the invention will be understood in more detail with respect to methods and configurations of operation together with other objects and advantages of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

1 shows a block diagram of a quadrature demodulator of the present invention. Preferably, the present demodulator with the component values shown operates at 455 KHz, but one skilled in the art will appreciate that it is possible to run at other frequencies without being limited to the frequencies. It is desirable to use an intermediate frequency of 455 KHz that is commonly used to use readily available and inexpensive ceramic filters and other components in the main body design.

The intermediate frequency I. F. amplifier 20 provides a limited I. F. signal to an exclusive OR circuit, or a node 22 connected to one input of the gate 24. Of course, the input of the I. F. amplifier 20 is driven by known circuit elements that form the front end of the receiver. The complete configuration of the front end varies considerably, but is not important for understanding the present invention. The same signal at node 22 is supplied to the input of current control active filter 26, and then the filtered signal is provided to node 28 connected to its output. Node 28 is connected to the input of phase shift network 30. The output of phase shift network 30 is also connected to node 32 connected to the other input of exclusive OR gate 24. The active filter 26 operates in conjunction with the phase shifting network 30 to provide a quadrature phase shifting mechanism for providing a quadrature signal in the present demodulator. The output of the exclusive OR gate 24 is connected to a node 30 that provides an input to the low pass filter 36, and the output 37 of the low pass filter 36 provides a reconstructed speech output signal of the demodulator. . One skilled in the art will appreciate that other types of logic gates may be substituted for the exclusive OR gate 24, but the exclusive OR gate used as a simultaneous phase detector has particular advantages within this embodiment which will be apparent later. have.

In a preferred embodiment, the circuitry is well implemented on a single integrated circuit comprising a current source 40 for biasing at node 41 a number of circuits including an exclusive OR gate 24 and a phase shift network 30. do. Current source 40 is a known design that preferably provides a relatively stable bias current through changes in battery voltage and temperature. However, active filter 26 requires a temperature compensated current source in this embodiment for reasons that will be apparent later. In order to provide suitable temperature stability, a temperature compensating network 42 is connected to the current source 40 and used to further compensate the temperature effect on the active filter as will be described in more detail below. The temperature compensation output is then connected to the active filter 26 at node 46 of the temperature compensation network 42.

In order to allow the demodulator to vary in response to changes in integrated circuit processing parameters and component tolerances, the resonant frequency of the active filter 26 is adjustable within the preferred embodiment. A frequency trim down network 44 is provided to lower the resonant frequency and is coupled to the temperature compensation network 42 at node 46A. A frequency trim up network 48 is provided to increase the resonant frequency of the active filter and is coupled to the active filter 26 at node 49. The temperature compensating network 42 also provides a bias to the phase shifting network 30 at node 46 to maintain a stable output level at node 32 against various changes in temperature, but to the phase shifting network 30. If the bias current is provided by another current source, it is not limited to the above.

In operation, a node that is at right angles (90 ° shifted phase) to the signal at node 22, the center frequency f _o of operating the demodulator, and changes about 90 ° phase as the input signal frequency is shifted from its center value. Active filter 26 operates in conjunction with phase shift network 30 to provide a signal at 32.

As shown in FIG. 2, the phase shift network 30 provides a constant phase shift at −90 ° like a curve 50 in the frequency range of at least approximately f ₁ to f _h , where f ₁ is an input signal. The lowest frequency normally flows, and f _h is the highest frequency at which the signal flows normally. The phase shift network 30 also includes an amplifying circuit to cause the limited output signal to be provided to the node 32 for processing by the exclusive OR gate 24.

The active filter 26 provides the frequency characteristics of the network in variable phase shift, by simulating a resonant circuit having a Q coefficient that is much larger than 1.0 and preferably greater than about 3.0. In a preferred embodiment, a Q factor of approximately 5.0-10.0 is used. The phase shift versus frequency characteristic curve of the active filter is shown as curve 52 in FIG. The curve increases in frequency over the range of f ₁ to f _h in the preferred embodiment, with an actual linear positive slope centered at about 180 ° at f _o . Of course, similar curves with a linear negative slope that decreases with increasing frequency can also be used as satisfactory results. The only difference in the variation that operates the demodulator is the 180 ° phase shift in the reconstructed audio. The slope of curve 52 is proportional to the Q of the active filter so that the slope increases with increasing Q. High Q coefficients (preferably approximately 5) are preferred for active filter 26, with higher Q causing higher slopes in curve 52, resulting in a demodulator for a predetermined amount of frequency deviation at node 22 This causes greater output voltage variation at. The active filter of the preferred embodiment has a Q value of approximately 10.

The active filter 26 and the phase shift network 30 become linear networks as long as the phase shift is within the main frequency range, and each phase shift curve of the network is added to obtain the resulting curve 54 directly. Curve 54 is plotted at a predetermined right angle at f _{o such} that active filter 26 associated with phase shift network 30 provides a valid simulation of the phase shift network of a conventional quadrature demodulator with an inductor based phase shift mechanism. Relationship and phase shift of the linear slope from f ₁ to f _h . As the active filter 26 and the phase shift network 30 are in series, those skilled in the art will appreciate that their respective positions can be switched without departing from the present invention, depending on suitable circuit modifications to properly interface. Could be. Of course, in some cases it is desirable to provide a limit output to node 32.

The demodulator operation of FIG. 1 can be understood with reference to FIG. 3 relative to FIG. 3A shows the limit IF signal at the nose 22. 3b to 3d assume that the signal of FIG. 3a is operated at frequency f _o . In addition, all signals in FIG. 3 are shown as limited signals for clarity, although they do not occur in the case of actual circuit operation. The signal passes through the active filter 26 and is 180 ° phase shifted as shown in FIG. 2 to generate a signal at node 28 as shown in FIG. 3B. Phase shift network 30 then provides a 90 [deg.] Phase lag to the signal at node 28 to generate a signal at node 32 as shown in FIG. Therefore, the signal at node 32 is perpendicular to the signal at node 22. Exclusive OR circuitry 24 processes the signals at nodes 22 and 32 to cause a signal at node 34, as shown in FIG. 3D. It can be seen that a doubling frequency occurs using an exclusive OR gate such as an output logic gate. This has particular advantages in the integrated circuit embodiment of the present invention that meets the corner frequency requirements of the low pass filter 36 to efficiently increase the recovered audio from the demodulator. Using the exclusive OR gate of this method, a demodulator is operated which is comparable to a conventional inductor demodulator with a square-based network based on a coil having a Q of 10.

The signal at node 34 passes through low pass filter 36 to provide an output signal at node 37. The low pass filter 36 acts as an integrator or an average circuit to produce an output that is the average value of the signal at node 34.

In FIGS. 3A and 3E-3G, the signal at node 22 (FIG. 3A) is in fact assumed that the main fruit tree is higher than f _o . In this case, the signal at node 28 is phase shifted by more than l80 degrees as shown in FIGS. 3E and 2. Phase shift network 30 phase shifts the signal by 90 ° to generate a signal at node 32 as shown in FIG. 3f. The synthesized signal at node 32 is phase shifted by at least 90 degrees.

As the signals at nodes 22 and 32 pass through the exclusive OR gate 24, the composite signal is shown in FIG. 3g. The signal of FIG. 3g apparently has a larger duty cycle than the signal of FIG. 3d and therefore has a larger average value. Thus, when the signal of FIG. 3g passes through the low pass filter 36, the output becomes a voltage greater than the voltage obtained when the signal of FIG. 3d is processed by the low pass filter 36. In this way, the frequency increases as the voltage increases. In a similar way, a decrease in output voltage causes a decrease in frequency.

In the preferred embodiment, the mutual conductance amplifier 60 is used to generate the active filter 26 and is connected as shown in FIG. Input capacitor 62 couples the signal at node 22 to the inverting input 64 of the cross-conductance amplifier. The mutual conductance amplifier 60 is connected to the output 64 via the resistor 68. The capacitor 70 is connected to AC ground at the output 66 of the mutual conductance amplifier 60. Output 66 is connected to node 28 to form the output of the active filter. The active filter has a band pass response according to the center frequency f _c given approximately below.

Where Gm is the mutual conductance of the mutual conductance amplifier. The equation indicates that both the center frequency and Q are mutual conductance Gm, and Q can be greater than 1.0. The equation furthermore shows that the center frequency of the network is stable for all temperatures involved and Q is also stable over temperature when the temperature coefficient of Gm reaches the temperature coefficient of the product of the resistor 68 and the capacitors 62 and 70. Do. Similar filter structures exhibiting anti-resonance at the center frequency by Gm can also be adjusted in frequency by varying the mutual conductance of the current and mutual conductance amplifiers.

As with the other figures, the circuit values shown in FIG. 4 are shown as embodiments, providing a valid Q of 10 in the demodulator at a center frequency of approximately 455 KHz within the preferred embodiment. By providing a mechanism for regulating the current in the mutual conductance amplifier 60, the mutual conductance is highly dependent on the current so that the center frequency is adjusted at the wafer level in the integrated circuit fabrication process. Frequency trim networks 46 and 48 are provided to adjust the frequency of the active filter by changing the current down or up, respectively, without changing the temperature compensated bias device effect. Thus, by providing a properly compensated bias current having a temperature coefficient equal to or opposite to the temperature coefficient of the product of resistor 68 and capacitors 62 and 70, the center frequency is adjustable over a wide range of frequencies, It becomes stable over temperature.

In FIG. 5, the phase shift network 30 and the frequency trim networks 44 and 48 and the active filter 26 (shown in dashed lines) are shown in more detail. The unregulated supply voltage is supplied at node 74 and is preferably approximately 1.5V. An regulated supply voltage of approximately 1.0V is applied at node 76. The unregulated supply voltage is applied to the emitters of transistors 80 and 82, which are provided to both collectors, respectively. The base of transistor 80 is not only connected to one collector thereof but also to the collector of transistor 84 and one terminal of capacitor 86. The base of transistor 82 is not only connected to one collector thereof but also to the collector of transistor 88 and the other side of capacitor 86. The emitters of transistors 84 and 88 are connected together, and are also connected to node 49, ground through resistor 108, and to the emitter of transistor 90. The collector and base of transistor 90 are connected together and grounded to each other.

The second collector of transistor 80 is connected to the base of transistors 92 and 94. The emitters of transistors 92 and 94 are grounded to ground. The collector of the transistor 94 is connected to the second collector of the transistor 82 and the node 28. Capacitor 70 is grounded at node 28 and resistor 68 is connected from node 28 to the base of transistor 84 which forms the input 64 of the mutual conductance amplifier. The base of transistor 88 is connected to node 46 and node 64 is connected to node 22 through capacitor 62 to complete the mutual conductance amplifier 26. The base of transistor 88 is biased at approximately 0.67V. In this embodiment, transistors 84 and 88 are X4 transistors (four times the nominal transistor size), and transistor 90 is also an X4 transistor. Transistors 80 and 82 are PNP transistors and the remaining transistors are NPN transistors of the active filter 26.

The operation of the mutual conductance amplifier is as follows. Transistors 84 and 88 are differentially connected to the base of transistor 84 forming the input of the amplifier. The tail current of the differential amplifier, the connection bias current through the emitters of transistors 84 and 88, is approximately 45 micro amps and is provided through frequency trim up network 48 and resistor 108. The base of transistor 88 is biased by frequency trim down network 44. Capacitor 86 provides compensation to ensure the stability of the amplifier. Transistors 80 and 82 are part of the current mirror, and together with transistors 92 and 94, transistors 80 and 82 provide parallel bias current to transistors 84 and 88 to the collector. By minimizing the number of P-N junctions between the supply and ground, the circuit's minimum operating voltage is kept to a minimum, and in fact the circuit performs with low battery voltages as low as 1.0V, allowing it to operate from a single battery cell.

The AC output current flowing from the collector junctions of transistors 82 and 94 to capacitor 70 and resistor 68 is proportional to the DC bias current of the differential amplifier and the AC input voltage at the base of transistor 84. The voltage at node 28 is delayed by approximately 90 ° at node 22, whose magnitude is proportional to the bias current. The feedback network, consisting of a resistor 68 and a capacitor 70, works with a mutual conductance amplifier to produce a bandpass response from input to output, the selectivity and center frequency of the response being programmable by adjusting the auxiliary current. .

As mentioned above, the center frequency of the active filter 26 can be adjusted by increasing or decreasing its bias current. The frequency can be adjusted upward by increasing the bias current by a frequency trim up network 48. The network 48 includes a plurality of resistors 100, 102, 104, and 106 having various values, each resistor having one terminal connected to the node 49. The resistor acts with a resistor 108 to set the current level of the mutual conductance amplifier. The other terminal of resistor 108 is directly grounded to ground to provide a minimum bias current level for amplifier 26. The second terminals of resistors 100, 102, 104, and 106 are trim pads 110, as well as emitters of NPN transistors 120, 122, 124, and 126, respectively. (112), (114), and (116). The collector and base of transistors 120, 122, 124, and 126 are all connected together and grounded, and the trim pad 128 is also grounded.

Transistors 120, 122, 124, and 126 are each used as a zener diode, which is a ground pad 128, trim pads 110, 112, It can be shorted out by applying an appropriate current pulse between 114 or 116. The actual programming technique is not very important to the present invention and depends on the setting and size of the zener diode in addition to the integrated circuit processing parameters. Known programming techniques may be used to short the zener diodes. Such trims can be chip carriers, DIP packages or other I.C. It may be performed after or before separating the integrated circuit wafer into individual dice for package and wire bonding within the package. Many benefits are provided by performing a frequency trim on the integrated circuit demodulator at the wafer edge. In the above step of processing the circuit, I.C. Can be trimmed rapidly with automated equipment that will be used to properly inspect each circuit. Also, since each circuit is processed on the same substrate in the same way, the drum parameters become more consistent and predictable in the circuit.

Since the zener bend (knee) of the diode is 6 V or more, it is not shorted, and when used for the low operating voltage of the preferred embodiment, the diode provides high impedance to ground. When shorted, the diode provides a resistance of approximately 100 ohms such that the resistors 100, 102, 104 and / or 106 can be selectively positioned in parallel with the resistor 108 such that the node ( The resistance from 49 to ground is effectively reduced, thereby increasing the bias current of the mutual conductance amplifier 60. In this way, the frequency of the active filter 26 can be increased over a range of approximately 100 KHz with component values shown at a resolution of about 5 KHz to achieve frequency tuning. This frequency adjustment can be easily automated with new computer controlled integrated circuit die probes, test and trim equipment. Specific values of resistors 100, 102, 104, and 106 are selected within the preferred embodiment to provide modulo two trimming. That is, resistor 106 causes an approximately 2% increase in the center frequency of filter f _o . Resistors 104, 102 and 100 cause a 4%, 8% and 16% increase in center frequency, respectively. This resistance is chosen in some combination to cause a total increase in center frequency between 2% and 30% with a fine resolution of 2%. In this embodiment the above 30% range is suitable to ensure an adequate upward trim of the frequency.

In a similar manner, the bias current for the amplifier 60 is reduced, thereby reducing the frequency of the active filter by the frequency trim down network 44, indicated by the dashed line in FIG. It is also desirable to observe the network 42 of FIG. 6 to understand the present circuit. Transistor 140 of temperature compensation network 42 has a collector and base connected to node 46. The emitter of transistor 140 is connected to the emitter of transistor 142 at node 46a and to one side of each resistor 144 (FIG. 6), 146, 148. The collector and base of transistor 142 are connected to ground as the second terminal of resistor 144. Second terminals of resistors 146 and 148 are connected to emitters and trim pads 154 and 156 of transistors 150 and 152, respectively. The base and collector of transistors 150 and 152 are connected to ground, so that transistors 150 and l52 are used as zener diodes in a similar manner to the zener diodes of network 48. Transistors 140, 150, and 152 are PNP transistors, while transistor 140 is an X2 NPN transistor. Transistor 142 is an X4 transistor.

The base of transistor 88 is biased with a voltage determined by the temperature compensated bias current, resistor 144 and diode connected transistor 140. The voltage can be adjusted by shorting transistors 150 and / or 152 such that the current of amplifier 60 is reduced by decreasing the voltage reference level at the base of transistor 88 and the frequency of active filter 26 is also reduced. Transistors 84, 88 so that the bias current flowing through transistor 108 has a temperature characteristic that matches the temperature characteristic of the compensation current used to bias the network formed by diode-connected transistor 140 and resistor 144. And 140 are matched to the device. Moreover, the required temperature compensation is maintained when the network is adjusted by shorting diodes 150 and / or 152. That is, since resistors 144, 146, 148 and 108, 100, 102, and 106 are all matched to the programmed structure, any zener diode in the trim network must be It acts to change the effective value of the resistor, but it is not affected by the temperature characteristics of the amplifier. That is, trim processing can also be easily automated.

The values of resistors 146 and 148 are selected to provide coarse frequency trim. Resistor 146 is trimmed when the deviation of the component value is in the middle range (approximately 15%) and resistor 148 is trimmed when the deviation is maximum (approximately 30%). Once cost reaming is complete, fine trimming processes trim up network 48 by selecting resistors 100, 102, 104, and / or 106 in the manner described above. By using the course down adjustment in addition to the fine down adjustment, the number of trim pads required for the integrated circuit is minimized, so that the board area on the integrated circuit can be used more efficiently. Those skilled in the art will appreciate that the present invention is optionally implemented in coarse up trim of frequency and fine down trim of frequency.

The frequency trimming process can be performed by monitoring the audio response of the demodulator. Various audio characteristics, including the top or bottom of the "S curve" of the demodulator, distortion and parallel noise can be used as an indicator of the correction trim. However, it can be seen that the trim method is virtually temperature independent. After the trim is completed, the integrated circuit wafer can be cut into respective dies for bonding and packaging.

The phase shift network is also shown in detail in FIG. The base of NPN transistor 160 forms an input of phase shift network 30 and is connected to node 28. Resistor 162 is connected between the collector of transistor 160 and a regular supply (node 76). The emitter of transistor 160 is connected to one side of resistor 164 and the other side of resistor 164 is grounded. One side of resistor 166 is connected to the collector of transistor 160 and the other side is connected to one side of capacitor 168 at node 170. The other side of capacitor 168 is connected to the emitter of transistor 160. These components provide the phase shift appearing at node 170 based on the phase shift network. The operation of the phase shift network is simple and described in the art.

The phase shift signal at node 170 is applied to a differential amplifier consisting of transistors 180, 182, 184, 186, and 188. Node 170 is connected to the base of transistor 180 and the emitters of transistors 180 and 182 are connected to the collector of transistor 186. The base and collector of the transistor 184 are connected to the base and node 41 of the transistor 186 and the emitters of the transistors 184 and 186 are grounded to ground. The base of the transistor 188 is connected to the node 46, and the collector is connected to the base of the transistor 182 and one side of the resistor 192. The other side of resistor 192 is connected to node 76. The emitter of transistor 188 is grounded through resistor 194. Transistors 180 and 182 have their collectors connected to nodes 32a and 31b, respectively. The collectors of transistors 180 and 182 are also connected to node 76 through resistors 196 and 198, respectively. Transistors 180, 182, 184, 186, and 188 are all NPN transistors, and transistor 186 is an X2 transistor in this embodiment.

The differential amplifier of phase shift network 30 acts as a conventional differential amplifier providing the inverted and non-inverted outputs to nodes 32a and 32b. Separating the signal in this way is good for increasing speed and reducing circuitry for processing with an exclusive OR gate. The differential amplifier also acts as a limiter that squares the signal at node 170 to ensure the highest possible reconstructed audio level, and the operation of the circuit is independent of the input signal level.

The remaining circuit shown in FIG. 5 shows I.F. The amplification degree serves as an interface in addition to providing. Transistors 200 and 202 form a differential pair with the emitter coupled together to the collector of transistor 204. The base of transistor 204 is connected to the base and collector of transistor 206 and to a current source 205 of 10 micro amps. The emitters of transistors 204 and 206 are grounded.

The base of transistor 200 passes through capacitor 210 to provide an input of a differential amplifier. It is connected to the amplifier 20. Bases of transistors 200 and 202 are connected to node 76 through resistors 212 and 214, respectively. The collectors of transistors 200 and 202 are connected to node 76 through resistors 216 and 218. The output of the differential amplifier is generated at the collectors of transistors 200 and 202 to provide inverted and non-inverted outputs 22a and 22b for processing with exclusive OR gates 24. Node 22b is also coupled to the base of transistor 220. The emitter of transistor 220 is grounded through resistor 222 and the collector is connected to node 76 through resistor 224 and node 22. Transistor 220 is connected as a common emitter amplifier with a gain of approximately 1/100 and used to reduce the signal level at node 22b to a level suitable for processing by active filter 26. Transistors 200, 202, 204, 206, and 220 are all NPN transistors, and transistor 204 is an X2 transistor.

In FIG. 6 the current source 40 and the temperature compensating network 42 are shown in detail. Unregulated power is provided at node 74 connected to the emitters of transistors 300 and 302. The bases of transistors 300 and 302 are also connected together, to the collectors of transistors 304 and 306. The base of transistor 304 is connected to the base and collector of transistor 308. The emitters of transistors 304 and 308 are grounded. The base of transistor 308 is connected to node 310 through resistor 314. The base of transistor 316 is connected to node 310 through resistor 318. The emitter of transistor 316 is grounded, and the collector of transistor 316 is connected to the emitter of transistor 306 through resistor 320.

The base of transistor 306 is coupled to one side of capacitor 324, the first collector of transistor 302, and the collector of transistor 326. The other side of capacitor 324 is grounded as an emitter of transistor 326. The base of the transistor 326 is connected to the second collector of the transistor 302 and the base and emitter of the transistor 330. The emitter of transistor 330 is grounded to ground through diffused current setting reference resistor 334. Transistors 300 and 302 are PNP transistors, and transistors 304, 308, 316, 326, and 330 are NPN transistors. In addition, the transistor 330 is an X4 transistor, and the transistor 308 is an X8 transistor. The collector of transistor 300 is connected to node 41 to form the output of the current source.

The current source is a bandgap basis reference circuit and operates as follows. Transistors 326, 330, 306, and 302, along with the value of resistor 334, flow through transistors 326 and 330 given the ratio of junction regions of transistors 326 and 330 as follows: Form a feedback loop that sets the reference current.

here;

k = constant of Boltzmann

T = Kelvin temperature

q = electron change

A = emitter area ratio of transistor 330 divided into emitter area of transistor 326

The bias voltage set by the reference circuit on the base of transistor 302 also biases another similar transistor connected to the node to mirror the reference current. Thus, the reference current is mirrored by the transistor 300, and the collector current of the transistor 300 includes the transistors 440, 442 and (442) of the exclusive OR gate 24 to provide a controlled current mirrored current source. 444 and the transistors 184 and 186 of the phase shift network 30 are biased.

When node 310 is connected to a logic high voltage, transistor 316 is turned on by the current flowing through resistor 318 and the collector of transistor 316 is saturated, thereby resistor 320. The end of the ground is grounded and the current source is turned on. When node 3110 is connected to a logic low voltage, transistor 304 and transistor 316 are turned off, removing the base bias from transistors 300 and 302, thus shutting off the current source.

The temperature compensating network 42 is also shown in detail in FIG. The emitter of transistor 350 and emitter of transistor 352 are connected to a battery voltage at node 74. The base of the transistor 350 is connected to the base of the transistor 302 of the current source 40 and the first collector of the transistor 350. The second collector of the transistor 350 is connected to the base and collector of the transistor 354 and the base of the transistor 356. The emitter of transistor 354 is grounded through ion implantation current setting reference resistor 360. Transistor 354 forms a compensation diode for the current mirror circuit formed of transistors 354, 350, 352, 356, and resistor 360. The emitter of transistor 356 is grounded and the collector of transistor 356 is connected to the first collector and base of transistor 352. A second collector of transistor 352 is connected to node 46 to provide an output of temperature compensation network 42. Transistors 350 and 352 are PNP transistors, and transistors 354 and 356 are matched NPN transistors, where transistor 354 is 10X larger in emitter area than transistor 356.

Temperature compensation circuitry to compensate for the nearly identical but negative temperature coefficients of the active filter mainly resulting from variations in resistor 68, capacitors 62 and 70, and transistor emitter resistance r _e and device current gain variation over temperature. (42) is designed to generate an output current with a positive temperature coefficient on the order of +9000 ppm per degree Celsius. Since the base current of transistor 350 is also supplied through transistor 306, the compensation network is controlled by node 310.

The operation of the temperature compensation network is as follows. A bias current that mirrors the reference current set by current source 40 flows from one collector of transistor 350 through injected resistor 360 and diode connected transistor 354 and the current flows through transistors 354 and 356 and The output current in the collector of the transistor 356 mirrored by the current multiplied by the current mirror formed by the combination of resistors 360 and also mirrored by the PNP transistor 352 to the output node 46 is set. Important for the design of a temperature compensated bias circuit is the output current with a temperature coefficient that can be varied widely by the appropriate choice of resistance values and mirror parameters, by deliberately using different resistance structures with different temperature characteristics of the current mirror circuit. Is to generate.

Thus, the diffused resistor 334 of the current source 40 forms the base of the NPN transistor and is made of the same diffuser having a temperature coefficient of approximately +1500 to +1800 ppm per unit of centigrade. Thus, the collector current of transistor 350 has a temperature coefficient (T.C.) of approximately +1700 ppm, which is a function of TO (300 degrees Kelvin). And the result of T and C of the resistance 334. In order to accurately compensate for temperature variations in the network 26, the voltage drop across the resistor 360 and the physical structure are selected to produce the required temperature characteristics. As will be explained mathematically, the T.C. Can be adjusted broadly by appropriately selecting the structures used to form the resistors 334 and 360 and other mirror parameters.

For the particular embodiment shown here, the sheet resists 2K ohms / square and approximately +4200 ppm T.C. An ion implanted resistive structure having is used to be supplied to the resistor 360.

The current in transistor 46 has T.C. according to the following equation.

here :

: 저항(334)이 주입될 경우에는 대략 -900ppm, 그것이 확산되는 경우에는 대략 +1700ppm인 트랜지스터(350)의 콜렉터 전류의 T.C.

TC of the collector current of transistor 350 which is approximately -900 ppm when resistor 334 is injected and approximately +1700 ppm when it is diffused

I1: Collector current of transistor 350 (according to resistor 334).

Vt: thermal voltage KT / q = 26mv at room temperature.

R = resistance (360)

Simplifying the above equation, the synthesized temperature coefficient of the current start node 46 is the temperature coefficient of the current I1 starting the collector of the transistor 350 + the predetermined logarithm of the current I1 or the boost factor (I1R / Vt) times + TC of resistor 360 And T.C. of thermal voltage It is expressed as a function of multiples of the difference between.

In this embodiment, a temperature coefficient of about +9000 ppm relative to the output current is made to compensate for the active filter. However, since a wide range of temperature coefficients can be supplied using published principles, the present temperature compensation network is not limited to the above preferred embodiment.

By substituting the above equation, a circuit redundancy with T.C. equal to the current of the collector of transistors 350 and 352 can be obtained using the resistors 334 and 360 of the same temperature coefficient. This is either the case where the two resistors are diffused (T.C. of resistance approximately +1700 ppm), injected (T.C. of resistance approximately +4200 ppm), or external carbon resistance (T.C. of resistance approximately 100 ppm).

Various ranges of current temperature coefficients can be achieved in the collector of transistor 352 by appropriately selecting various combinations of the resistive (or other temperature dependent resistive elements, such as thermistors). For example, if resistor 334 diffuses to a surface area, positive T.C. Can be achieved at a predetermined temperature of approximately 3200 ppm or more without the need to modify the circuit of FIG. In this embodiment, the equation can be simplified as follows:

By appropriately adjusting the values of the current I1 and the resistance 360 (R), the predetermined T.C. Can be obtained. Similar results occur when resistor 334 is superficial and resistor 360 is injected, except that a smaller value of resistance 360 is required.

A similar interpretation for diffused resistance 334 and surface resistance 360 is as follows:

Tj, negative or positive T.C. Either of which can be obtained and can be easily implemented if virtually 0.0 ppm is desired.

Another important embodiment is obtained when resistor 334 is injected and resistor 360 is diffused. In this case, the equation can be simplified as

And, T.C. can be configured to be virtually any desired negative value required.

Various substitutions of the above interpretation can be carried out with various results. In each case, however, it can be seen that the multiplication of the temperature coefficient occurs as a controllable factor of RI1 / Vt used to raise or lower the T.C. as required. This means that the T.C. obtainable with the use of the present invention is not limited to either T.C. of either of the resistive components.

In FIG. 7, a good exclusive OR gate 24 is shown in detail according to the low pass filter 26. The normal supply voltage at node 76 is connected to the collectors of transistors 400, 402, and 404. The collectors of transistors 410, 412, and 414 are also connected to node 76 through resistors 420, 422, and 424, respectively. The emitter of transistor 400 is connected to the emitters of transistors 410 and 430 as well as the collector of transistor 440. The emitter of transistor 402 is connected to the emitters of transistors 412 and 432 as well as the collector of transistor 442. The emitter of transistor 404 is connected to the emitters of transistors 414 and 434 as well as the collector of transistor 444. The emitters of transistors 440, 442, and 444 are all grounded, and the base is connected to node 41.

The collector of transistor 430 is connected to the collector of transistor 410 and the base of transistor 434. The base of transistor 430 is connected to node 22a. The bases of transistors 400, 402, and 404 are all connected to node 450, which is connected to a reference source of 0.82V (not shown). The collector of transistor 412 is connected to the collector of transistor 412 and the base of transistor 414. The base of transistor 432 is connected to node 22b. Nodes 32a and 32b are connected to the base of transistors 412 and 410 respectively. The collector of transistor 434 is the output of the exclusive OR gate and is coupled to the collector and node 34 of transistor 414.

Exclusive OR gate 24 operates as follows. Transistors 440, 442, and 444 provide a bias current to the gate. Transistors 400, 410, and 430 act as NOR gates to provide a low output at the collector of transistor 430 when node 22a or 32b is logic high. Similarly, transistors 402, 412, and 432 act as NOR gates that provide a low output at the collector of transistor 432 when node 22b or 32a is logic high. Transistors 404, 414, and 434 also operate on the output signals of the two NOR gates to provide a logic low output at the collector of transistor 434 when either one of the outputs of the two NOR gates is high. It acts as a working NOR gate.

One side of the resistor 504 connected to the node 37 and the resistor 500 connected to the node 34 to form an output node, the resistors 500, 502 and 504 connected in series with one side. The low pass filter 36 as a simple three-stage passive RC trapezoidal network composed of) is also shown in detail in FIG. Capacitor 510 is grounded at the junction of resistors 500 and 502. Capacitor 512 is grounded to ground at the junction of resistors 502 and 504. Capacitor 514 is grounded at node 37 to ground.

Low pass filter 36 provides an attenuation of about 53 dB at 455 KHz and an attenuation of about 70 dB at 910 KHz. It will be appreciated that this is an appropriate level of filtering for various applications, but in some cases it may not be an appropriate level of filtering. Another stage of either passive or active filtering is, of course, added or not added to the integrated circuit. Such filtering can easily be accomplished in an audio amplification stage that typically conforms to a low pass filter.

The demodulator described above is fully integrated on a single integrated circuit chip fed to a conventional bipolar linear integrated circuit fabrication process. The demodulator provides comparable performance to that of a conventional inductor based demodulator that provides a nominal audio output level of about 20 mV between peaks for a deviation of 2.5 KHz. It is stable within ± 5% of the center frequency -20 to 60 degrees Celsius. The circuit operates on battery voltages from 1.0 to 3.0V and consumes less than 75 micro amps of current. In addition, expensive, unreliable, bulky inductors are eliminated entirely without compromising performance, thereby significantly reducing cost, size, and weight, further increasing reliability, and eliminating labor-intensive and expensive handwork of inductors.

When certain PNP and NPN junction transistor devices are described in connection with the present invention, it will be apparent to those skilled in the art that other specific circuit devices may be used without departing from the spirit and scope of the present invention. For example, various circuits using NPN transistors can be equally supplied to PNP transistors. Similarly, analog circuits supplied in various field effect element technologies can be used for various present circuits. The present invention includes such embodiments.

Thus, an apparatus which satisfactorily satisfies the object and advantages according to the present invention has been clearly described above. When the subject matter is described in connection with a particular embodiment, various alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing. Accordingly, all such alternatives, modifications and variations may be permitted when the invention is within the spirit and scope of the appended claims.

Claims (10)

A circuit arrangement for providing a current having a control temperature coefficient, comprising: a first resistance means 334 having a first predetermined temperature coefficient, and connected to the first resistance means 334, the first predetermined temperature Current source means 302, 306, 324, 326, 330 for supplying a first current having a first temperature coefficient that varies with the coefficient, and a current mirror that receives the first current as a reference current for generating a mirror current A second resistor connected to the means 350, 352, 354, 356 and the current mirror means 350, 352, 354, 356 and having a second predetermined temperature coefficient different from the value of the first temperature coefficient. Means 360, wherein the mirror current has a temperature coefficient that varies according to a combination of the first predetermined temperature coefficient and the non-zero algebraic multiple of the second predetermined temperature coefficient. A current providing circuit device. 2. The current providing circuit device according to claim 1, wherein said first resistance means (334) comprises a diffusion resistor. 2. The current providing circuit arrangement according to claim 1, wherein said first resistor means (334) comprises an injection resistor. The current providing circuit device according to claim 1, wherein said first resistance means (334) comprises an external resistance element. 5. The current providing circuit device of claim 4, wherein the external resistor element comprises a thermistor. 2. The current providing circuit device according to claim 1, wherein said second resistance means (360) comprises a diffusion resistor. 2. The current providing circuit device according to claim 1, wherein said second resistance means (360) comprises a resistor. 2. The current providing circuit device according to claim 1, wherein said second resistance means (360) comprises an external resistance element. 9. The current providing circuit device of claim 8, wherein the external resistance element comprises a thermistor. 2. The current providing circuit arrangement according to claim 1, wherein said current mirror means comprises a current mirror which multiplies the current.

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