KR940006590B1 - Multi-tv r.g.b. color signal control circuit - Google Patents

Abstract

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Description

Multi-Mode Color Control Circuit

1 is a block diagram showing a conventional multi-mode color control circuit.

2 is a block diagram illustrating a multi-mode color control circuit in accordance with the present invention.

3, a and b are detailed circuit diagrams showing a multi-color control circuit according to the present invention.

4A and 4B are output waveform diagrams showing a multi-mode color control circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: drive unit 12: R color signal drive unit

14: B color signal driver 16: G color signal driver

20,22,24,26: Output section 30,32,34,36: Buffer section

40, 40-1, 40-2, 40-3: control circuit 41: current amplifier

50: multi-bias voltage control circuit 42-1, 42-2, 42-3: voltage setting section

51: clock generating circuit 43-1, 43-2, 43-3: switching unit

52: counting circuit 44-1,44-2,44-3: voltage output unit

53: mode separation unit 52-1, 52-2: flip-flop

53-l, 53-3,53-5,53-6: NAND gate 53-2,53-4,53-7: Inverter

R1 to R9, R50 to R81, R00: Resistor C1 to C14, C50 to C64: Capacitor

Q1-Q12, Q50-Q53: Transistors ZD50-ZD53: Zener diode

D50PD52: Diode VR50 to VR59: Variable resistor

PB, SW1 to SW9: Switch L: Latch

The present invention relates to all systems capable of image processing with R, G, and B color signals. More specifically, the present invention relates to beam currents of R, G, and B color signals by bias voltages of R, G, and B color signals applied to cathode ray tubes. The present invention relates to a multi-mode color control circuit that can realize various colors of high purity and high definition due to maintaining a stable white color.

Conventionally, as shown in FIG. 1, an output unit 2 is connected to the output side of the drive unit 1 in which the R, G, and B color signals are driven, and R, G, B are connected to the output side of the output unit 2. The cathode ray tube 3 which displays the color signal on the screen is connected. At this time, the luminance unit 4 for representing the contrast of the screen is connected to the cathode ray tube 3. In the conventional circuit diagram configured as described above, the R, G, and B color signals are generated by the drive unit 1, and the generated color signals are amplified by a sufficient signal for driving the cathode ray tube 3 through the output unit 2 and output. do. The output signal of the output unit 2 is applied to the cathode of the cathode ray tube 3 to reproduce the color signal on the screen of the cathode ray tube 3. At this time, the sharpness of the screen is controlled by the luminance signal output from the luminance unit 4. That is, the bias potentials of the R, G, and B color signals applied to the cathode ray tube 3 are fixed, and by changing the luminance potential of the cathode ray tube 3, the amount of beam current applied to the cathode ray tube 3 is adjusted, so that the brightness of the screen is adjusted. Is controlled. Therefore, by controlling the luminance of the R, G, and B color signals in order to sharpen the screen, a difference in the beam current applied to the cathode ray tube of the R, G, and B color signals is generated. Difficult to maintain level The instability of the white color level due to the luminance control of the R, G, and B color signals has a problem that it is difficult to maintain high purity colors.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to adjust the difference in the beam current generated when controlling the luminance of the R, G, and B color signals in order to sharpen the screen. It is intended to provide a multi-mode color control circuit that maintains a stable white color level by varying the voltage.

A feature of the present invention for achieving the above object is a drive for driving the R, G, B color signals of the input image information, a pull unit for amplifying each color signal driven by the drive unit to a sufficient level, and the output A multi-mode color control circuit comprising a cathode ray tube for displaying a negative R, G, and B color signal on a screen, and a luminance unit for controlling luminance by outputting a control signal to one side of the cathode ray tube, the color signal output from the output unit: A buffer section for shaping; A multi-bias voltage control circuit for counting the driving pulses oscillated by the switching operation and outputting a plurality of signals for distinguishing modes by logically combining the counting signals; The control circuit for varying the voltage value applied to the color signal according to the mode as a plurality of signals to distinguish the mode input from the multi-bias voltage control circuit when the brightness is adjusted by applying a voltage to the color signal shaped by the buffer unit It is at that point.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a multi-mode color control circuit according to an embodiment of the present invention, which is generated in the drive unit 10 at the output side of the drive unit 10 in which R, G, and B color signals for image information are generated. The output unit 20 which is sufficiently amplified color signal is connected. A buffer circuit 30 for outputting R, G, and B color signals is connected to an output side of the output unit 20, and a control circuit for controlling a multi-color color signal on the output side of the buffer unit 30 ( 40) is connected. At this time, the cathode ray tube 60 to which the beam current is increased in proportion to the bias voltage of the R, G, and B color signals output from the control circuit 40 is connected to the output side of the control circuit 40. On the other hand, the multi-bias voltage control circuit 50 is connected to the input side of the control circuit 40, the bias voltage of the R, G, B color signals applied to the cathode ray tube 60 is variable.

The multi-bias voltage control circuit 50 includes a clock generation circuit 51 that oscillates and outputs a driving pulse, and an output side of the clock generation circuit 51 is counted to count an output pulse of the clock generation circuit 51. And a mode separator 53 connected to the output side of the counting circuit 52 and outputting a mode control signal using the counted output signal.

3 (a) and 3 (b) are detailed circuit diagrams showing a multi-mode color control circuit according to the present invention, the configuration of which is shown in detail. Here, the amplifying transistor Ql of the output unit 22 for amplifying the R signal output from the R color signal driver 12 of the drive unit 10 is connected to the output side of the R color signal of the R color signal driver 12, The emitter resistor Rl and the high frequency compensation capacitor C1 are connected to the emitter side of the transistor Ql. On the other hand, the amplifying transistor Q2 of the output section 22 is connected to the collector side of the amplifying transistor Ql by being turned on / off by the constant voltage Vcc3, and outputted to the base side of the transistor Q2. The noise removing capacitor C4 of the unit 22 is connected. In addition, a bypass resistor R4 and a pike detecting coil Ll are connected in series between the collector side of the amplifying transistor Q2 and the constant voltage Vcc2. On the output side of the output unit 22 for the R color signal, the transistors Q7 and Q8 of the buffer unit 32 for the R color signal simultaneously turned on / off by the output signal to the collector of the transistor Q2. ) Is coupled, and a coupling capacitor C7 is connected to the outputs of the buffer transistors Q7 and Q8.

At this time, in order to vary the bias voltage applied to the cathode ray tube 50, the control circuit 40 connected to the output side of the capacitor C7 of the buffer unit 32 is a current whose current is amplified by the variable resistor VR50 for luminance control. A voltage setting section 42-1, 42-2, 42-3 connected to an amplifying section 41, an output side of the current amplifying section 41 and set various voltages; 42-1, 42-2 and 43-3, which are connected to the output side of 42-2, 42-3, and output variously set voltages, and the switching unit 43-1. ), (43-2) and (43-3) are connected to the output side of each switch SW1-SW9 so that the output voltages of the switching sections 43-1, 43-2, and 43-3 are negative. It consists of voltage output parts 44-1, 44-2, and 44-3 which are controlled to be applied to the pipe 60.

Here, the distribution resistor R50, the luminance control variable resistor VR50, and the distribution resistor R51 are connected to the input side of the constant voltage Vcc4 of the current amplifier 41 in order. The input side of R50 is connected to the collector side of transistor Q50 of current amplifying section 41 for current amplification. A capacitor C52 for determining the time constant of operation is connected to the base side of the transistor Q50, and a voltage setting for setting bias voltages of R, G, and B color signals is set on the emitter side of the transistor Q50. The sections 42-1, 42-2, and 42-3 are connected

That is, the zener diode ZD50 of the voltage setting unit for maintaining the set voltage is connected to the heater side of the transistor Q50 of the current amplifier 41, and a resistor R52 directly coupled to the zener diode ZA50, R53, R54 and variable resistors VR51, VR525, and VR53 are connected in parallel in order. The switching unit outputs the voltage set by the variable resistors VR51, VR525, and VR53 to the output sides of the variable resistors VR51, VR525, and VR53 of the voltage setting units 42-1. It is connected to each switch SW1, SW2, and SW3 of 43-1, and the switching part 43-1 is provided on the output side of each switch SW1 to SW3 of this switching part 43-1. The voltage output unit 44-1 to which the voltage output from the cathode ray tube 60 is applied is connected.

The voltage output section 44-1 connected between the output side of the condenser C7 of the buffer section 32 and the output of the switching section 43-1 of the control circuit 40 is connected to the bypass resistor R65. The blocking diode D50, the capacitor C58, the bias resistor R6, the amplifying transistor Q51 amplified by the voltage output from the switching unit 43-1, and the ground resistor R68 are sequentially formed. It is connected.

The driving units 14 and 16, the output units 24 and 26, the voltage setting units 42-2 and 42-3 of the control circuit 40, and the switching units 43-2 and 43 for the G color signal and the B color signal. -3), the voltage output section 44-2, 44-3 includes the oscillation section 12 for the R color signal, the output section 22, the voltage setting section 42-1 of the control circuit 40, and the switching section. 43-1 and the voltage output section 44-1. In the clock generation circuit 51 of the multi-voltage bias control circuit 50, the resistor R100 to which the constant voltage Vcc5 is applied and the switch PB are connected in series, and the resistor Rl00 is connected to the input terminal between the switches. The other input terminal has a latch portion L whose voltage level is fixed high by the constant voltage Vcc5. The latch portion L is a general circuit consisting of two NAND gates.

In addition, the counting circuit 52 connected to the output side of the clock generation circuit 51 is composed of two flip-flops 52-1 and 52-2 connected to the output side of the latch portion L in the clock generation circuit 51. The output signal of the flip-flop 52-1 is input to the flip-flop 52-2. The mode separator 53 is connected to the output side of the counting circuit 52.

That is, the counting circuit 52 has a NAND gate 53-1 to which two output signals of the flip flops 52-1 and 52-2 are input, and an output of the flip-flop 52-1 is an inverter 53-2. NAND gate 53-3, which is inverted through the input and output of the flip-flop 52-2, and the output of the flip-flop 52-1 are input as they are, and the output of the flip-flop 52-2 is The output is the NAND gate 53-5 inverted through the inverter 53-4, and the outputs of the two flip-flops 52-1 and 52-2 are respectively through the inverters 53-2 and 53-4. Inverted input NAND gate 53-6 is configured, and the output of the NAND gate is inverted by the inverter 53-7 and connected to be input as a reset signal of the flip-flops 52-1 and 52-2. have.

Here, the output signals c, d, and e of the NAND gates 53-1, 53-3, and 53-5 are switched to each switch 43-1 in the control circuit 40 of FIG. 2A. And flip-flop of the counting circuit 52 by the output signal F of the inverter 53-7, which is applied to the control side of the switches SW1 to SW9 of (43-2) and (43-3). (52-1) and (52-2) are reset.

In Fig. 2, reference numerals C10 to C15, C50, C51, and C56 to C63 are voltage stabilizing capacitors, and R64, R70, R74, R76, R80, and R81 are voltage protection resistors.

In the present invention configured as described above, the R, G and B color signals driven by each of the R, G and B color signal drivers 12, 14 and 16 in FIG. 3A are output parts 22, 24 and 26, respectively. As the amplifying transistors Ql, Q3, and Q4 are driven, the transistors Q2, Q4, and Q6 driven by the constant voltage Vcc3 are operated. At this time, noise input by the application of the constant voltage Vcc2 is removed by the capacitors C4, C5, and C6, respectively.

The R color signal amplified by the transistors Q2, Q4, and Q6 while the amplifying transistors Q1, Q3, and Q5 are driven, respectively, is a buffer transistor of the buffer unit 32. In (Q7) and (Q8), the G color signal is supplied to the buffer transistors Q9 and Q10 of the buffer unit 34, and the B color signal is supplied to the buffer transistors Q11 and Q12 of the buffer unit 36, respectively. The R, G, and B color signals respectively output from the buffer transistors Q7 to Q12 are applied to the cathode ray tube 60 through coupling capacitors C7 to C9, respectively.

At this time, the bias voltages of the R, G, and B color signals applied to the cathode ray tube 60 are stabilized by the capacitors C10 to C15 of the buffer sections 32, 34, and 36. A process of varying the bias voltage of the R, G, and B color signals applied to the cathode ray tube 60 according to the luminance adjustment of the R, G, and B color signals will be described below.

When the luminance of the R, G, and B color signals is controlled by the variable resistor VR50 of the current amplifier 41 of the control circuit 40, the current amplifier transistor Q50 of the current amplifier 41 is controlled. Current is amplified. At this time, the time constant of the transistor Q50 is determined by the capacitor C52 connected to the base side of the current amplifying transistor Q50.

On the other hand, the transistors (ZD50 to ZD52) of the voltage setting units 42-1, 42-2, and 42-3 connected to the emitter side of the transistor Q50 of the current amplifier 41 The emitter side of Q50) is always kept constant at the set voltage of the zener diodes ZD50 to ZD52.

At this time, the set voltage of the zener diode ZD50 is divided by the resistor R53 and the variable resistor VR51 of the voltage setting unit 42-1, and the set voltage of the zener diodes ZD5l and ZD52 is the same as the resistor. The voltage is divided into different levels by the R54 and the variable resistor VR52, the resistor R55 and the variable resistor VR53. That is, the emitter side voltage of the transistor Q50 is divided into bias voltages of different levels under the control of the variable resistors VR51 to VR53 and applied to the switches SW1 to SW3 of the switching section 43-1.

Similarly, the set voltage of the zener diode ZD51 of the voltage setting section 42-2 is divided by the resistors R57 to R59 and the variable resistors VR54 to VR56 at different levels of bias voltages, and the divided voltage is divided. The applied voltage is applied to each switch SW4 to SW6 of the switching section 43-2. The set voltage of the zener diode ZD52 of the voltage setting section 42-3 is divided by the bias voltages of different levels by the resistors R61 to R63 and the variable resistors VR57 to VR59, respectively. Is applied to the switches SW7 to SW9.

The switches SW1 to SW9 of the switching sections 43-1, 43-2, and 43-3 are controlled by the multiple bias control circuit 50. This will be described with reference to FIG. 3 (b).

The pulse is generated by the resistor R100 and the switch PB of the clock generation circuit 51 of the multi-bias control circuit 50. At this time, since the contact noise is generated when the switch PB is switched, the latch unit L is configured between the switch PB and the resistor R100. When the switch PB is turned on, each potential of the node applied to the resistor R100 is applied to the latch portion L of the clock generation circuit 51 to remove noise, and thus the resistor R100 and the switch PB. The clock pulses are applied to the flip-flops 52-1 and 52-2 of the counting circuit 52 by the clock pulses. The flip-flops 52-1 and 52-2 of the counting circuit 52 are asynchronous counters and are output as shown in Table 1 below.

TABLE 1

Ignition Force Signal of Mode Separation Unit

The output signal a of the flip-flop 52-1 and the output signal b of the flip-flop 52-2 of the counting circuit 52 are applied to the mode separating unit 58, and the mode separating unit ( 53) logically combines the applied signals and outputs signals corresponding to three modes.

That is, when the output signal a of the flip-flop 52-1 and the output signal b of the flip-flop 52-2 are the low signal L at the same time, the NAND gate 53 of the mode separator 53 is used. The output signal (c) of -1 becomes the high signal (H), and the output signal (a) of the flip-flop (52-1) is the low signal (L) signal, so that the inverter moves to the input side of the NAND gate 53-3. The high signal H inverted by 53-2 is input to the low signal L of the flip-flop 52-2, and the output signal d of the NAND gate 53-3 is the low signal L. Becomes In addition, the output signal e of the NAND gate 53-5 is the inverted high signal H of the flip-flop 52-2 by the inverter 53-4 and the low signal of the flip-flop 52-1. The low signal L is obtained by (L).

At this time, the high signal H inverted by the inverters 53-2 and 53-4 is applied to the input side of the NAND gate 53-6, so that the output of the NAND gate 53-6 is Becomes the low signal L, and the low signal L is inverted by the inverter 53-7 and applied to the flip-flops 52-1, 52-2 to flip the flip-flops 52-1, ( 52-2).

The output signal c of the NAND gate 53-1 of the mode separation unit 53 is applied to the switches SW1 to SW3 of the switching unit 43-1 to which the bias voltage of the R color signal is applied, and the mode separation is performed. The output signal d of the NAND gate 53-3 of the unit 53 is applied to the switches SW4 to SW6 of the switching unit 43-2 to which the bias voltage of the G color signal is applied, and the NAND gate 53-. The output signal e of 5) is applied to the switches SW7 to SW9 of the switching section 43-3 in which the bias voltage of the B color signal is varied.

As described above, the switching units 43-1, 43-2, and 43-3 are controlled by the control signals c, d, and e output from the mode separation unit 53 of the multi-bias voltage control circuit 50. ) Is on / off, and the variable resistor VR51 of the voltage setting sections 42-1, 42-2, 42-3 is turned on / off by the switching units 43-1, 43-2, 43-3. The voltage set by ˜VR59 is applied to the voltage output units 44-1, 44-2, 44-3 through the switches SW1 to SW9 in the switching units 43-1, 43-2, 43-4. do. At this time, the voltage output from the voltage setting units 42-1, 42-2, 42-3 is switched on by the switching units 43-1, 43-2, 43-3 by the capacitors C5, C54, C56. Noise generated when turned on / off is removed.

On the other hand, the voltage output section 44 of the voltage setting section 42-1, 42-2, 42-3 output by the switches SW1 to SW9 of the switching sections 43-1, 43-2, 43-3. The potential difference between the collector side emitter side of the transistors Q51, Q52, Q53 is determined by the base potentials applied to the transistors Q51, Q52, Q53 of -1, 44-2, 44-3. At this time, the gains of the transistors Q51, Q52, and Q53 are determined by the ground resistors R68, R73, and R78 connected to the collectors of the transistors Q51, Q52, and Q53.

The bias voltage of the R color signal applied to the cathode ray tube 60 may include a resistor R65, a diode D50, a resistor R66, and a transistor Q51 of the voltage output unit 44-1 of the control circuit 40. Is determined by the potential difference between the collector side and the emitter side, and at this time, the bias voltage of the R color signal output by the capacitor C58 is stabilized.

In addition, the bias voltage of the G color signal applied to the cathode ray tube 60 may also include the resistor R70, the diode D51, the resistor R71, and the transistor Q52 of the voltage output unit 44-1 of the control circuit 40. Is determined by the potential difference between the collector side and the emitter side, and the bias voltage of the B color signal is also determined by the voltage output section 44-3 of the control circuit 40 in the same manner.

As described above, in the present invention, the R, G, and B color signals output from the drive unit 10 are transmitted by the transistors Q1, Q2, Q3, Q4, Q5, and Q6 of the output units 22, 24, and 26. The amplified R, G, and B color signals are respectively input to the cathode ray tube 60 through the transistors Q7, Q8, Q9, Q10, Q11, and Q12 of the buffer units 32, 34, and 36.

At this time, the current is amplified by the transistor Q50 of the current amplifier 41 according to the value of the variable resistor VR50 set to adjust the brightness of the current amplifier 41 of the control circuit 40. The luminance appearing in the cathode ray tube is controlled.

Further, the voltage setting sections 42-1, 42-2, 42 of each of the R, G, and B color signals connected to the emitter side of the transistor Q50 of the current amplifier 41 of the control circuit 40. The voltages applied to the zener diodes ZD50, ZD51, and ZD52 of -3) are the voltage setting sections 42-1, 42-2, and 42-3 of the respective R, G, and B color signals. The voltage divided by the resistors R53 to R63 and the variable resistors VR51 to VR59 and divided by the variable resistors VR to VR59 is output from the mode separation unit 53 of the multi-bias voltage control circuit 50. Applied to the switches SW1 to SW9 of the switching units 43-1, 43-2, and 43-3 turned on / off by the signals c, d, and e, and the switching units 43-1 and 43 The voltage passing through -2, 43-3 is applied to the cathode ray tube 60 through the voltage outputs 44-1, 44-2, 44-3. That is, the beam current generated by adjusting the luminance of the R, G, and B color signals can be constantly adjusted as shown in (a) and (b) of FIG. 4 by varying the bias voltage of each color signal applied to the cathode ray tube 60. have.

(A) of FIG. 4 is a voltage change curve according to the degree of change of the variable resistor VR50 of the current amplifier 41 in the control circuit 40 of FIG. 3 (a), and (b) of FIG. Figure 4 shows the change in luminance according to the voltage change in (a). That is, due to the change in the variable resistor VR50, the voltage and luminance applied thereto have a proportional relationship.

As described above, the present invention removes the difference in the beam current generated by the brightness control of the R, G, and B color signals by the bias voltage applied to the cathode ray tube, thereby making the white color generated by the difference in the beam current stable. Therefore, the color coordinate system is kept uniform all the time, so that the color of the screen can be realized clearly and with high purity.

Claims (4)

A drive for driving the R, G, and B color signals of the recall information input; an output unit for amplifying each color signal driven by the drive unit to a sufficient level; and a cathode ray for displaying the R, G, B color signals of the output unit on a screen; A multi-mode color control circuit comprising a tube and a luminance unit for controlling a luminance outputting a control signal to one side of the cathode ray tube; A buffer unit for shaping the color signal output from the output unit; A multi-bias voltage control circuit for counting driving pulses oscillated by the switching operation and outputting a plurality of signals for distinguishing modes by logically combining the counting signals; When the brightness is adjusted by applying a voltage to the color signal shaped by the buffer unit, a plurality of signals for distinguishing the modes inputted from the multi-bias voltage control circuit. A multi-mode color control circuit comprising control circuits for outputting R, G, and B color signals. The method of claim 1, wherein the control circuit; A current amplifying unit configured to output a current for the luminance signal by including a first variable resistor for applying a color signal to vary the current representing the luminance and a transistor for amplifying the current varied by the variable resistor; The first voltage setting unit divides the set voltage to be applied to the R color signal by applying the current output from the current amplifier to at least one variable resistor, and the current output from the current amplifier is applied to at least one variable resistor. The second voltage setting unit divides the set voltage to be applied to the G color signal, and the third voltage setting divides the set voltage to be applied to the B color signal color signal by applying the current output from the current amplifier to at least one variable resistor. A voltage setting section for setting a voltage for luminance to be applied to the R, G, and B color signals by an additional configuration; One side is connected to an output side of each variable resistor of the first voltage setting unit, and is composed of a number of switches corresponding to the variable resistance of the first voltage setting unit switched by a signal for distinguishing a mode output from the multi-bias voltage control circuit. One side of the second voltage setting unit is connected to a first switching unit and an output side of each of the variable resistors of the second voltage setting unit, and is switched by a signal for distinguishing modes for distinguishing modes output from the multi-bias voltage control circuit. A second switching unit comprising a number of switches corresponding to a variable resistor and one side of the third voltage setting unit are connected to an output side of each variable resistor and switched by a signal for distinguishing modes output from the multi-bias voltage control circuit. A third switching unit comprising a number of switches corresponding to each of the variable resistors of the third voltage setting unit; By a switching unit which is switched by a signal to identify the mode in which the output from the multi-bias voltage control circuit; And a voltage output part outputted to the cathode ray tube after the voltage set by the voltage setting part is switched and applied to the R, G, and B color signals output from the output part. The circuit of claim 1, wherein the multi-bias voltage control circuit comprises:; A clock generation circuit configured to generate a clock pulse as the constant voltage is switched and to output a signal preventing contact noise generated during switching; The clock signal generated by the clock generation circuit is input to the first and second flip flops, and the output of the first flip flop to which the output signal of the latch unit is applied to the input side is applied to the second flip flop. A counting circuit for counting the clock signal by being output as an output signal and outputting the second flip-flop to which the first output signal is applied to the input side as a second output signal; And a mode separator configured to logically combine the first output signal and the second output signal to output a plurality of signals for separating modes, and to output a reset signal to the counting circuit. The method of claim 3, wherein the mode separator comprises: a first NAND gate outputting a high signal when both the first and second output signals of the counting circuit are low signals; and a first inverter inverting the first output signal. And a second NAND gate for outputting a high signal when the output signal of the first inverter and the second output signal are both low signals, a second inverter for inverting the second output signal, and the first output signal. And a third NAND gate outputting a high signal when the outputs of the second inverter are both low signals and a fourth NAND gate outputting a high signal when the outputs of the first inverter and the second inverter are both low signals And a third inverter for inverting the output signal of the fourth NAND gate and outputting the inverted signal as a reset signal of the reset circuit of the counting circuit.

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