KR940006268B1 - Data processing method in optical storage device - Google Patents

Abstract

searching for data recorded in a disk; if there is a desired address data block, buffering an address data in a static RAM through a digital signal processor; repeatedly correcting the address data; transferring the data stored in the static RAM to a host, thereby rapidly performing error correction.

Description

Data processing method in optical storage device

1 is a circuit block diagram of the present invention.

2 is an SRAM memory diagram of the present invention.

3 is a flow chart diagram of the present invention.

4 is a detailed view of the digital signal processor of the present invention.

* Explanation of symbols for main parts of the drawings

1: Host Central Processing Unit 2: Host Adapter

3: SRAM 4: Digital Signal Processor

5: microcomputer 6: descrambling

7: sync detector 8: clock and timing generator

9: Header / Sub Header Register 10: Error Correction Block

14: RA Register 15: Write Address

16: Error correction check and error detection check generator

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to data fast processing in a device that extracts data from an optical storage device and sends it to a host. In particular, the present invention relates to a host by decoding a data at a high speed by a hardware approach so that the data can be read in a short time and have a desired reliability. A data processing method in an optical storage device for transmitting.

In the case of data used in the memory system at the time of error correction of data, an error of 1 byte can be fatal to its contents, so accurate data is required as much as possible. In the actual decoding system, however, error correction is unsatisfactory as a single correction.

In view of the foregoing, the present invention has been made so that error correction can be performed accurately within a short time by performing no time delay while performing repeated error correction, which will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a circuit configuration of the present invention, in which the host central processing unit 1, the host adapter 2, the SRAM 3, the digital signal processor 4, and the microcomputer 5 are shown. To the optical storage device.

Here, the host CPU 1 and the host adapter 2 read data from the optical storage device with light and write the data into the SRAM 3.

The SRAM 3 should be able to accept the decoded data at a speed higher than the transmission speed.

Also, in the case of processing data in block units, in order to obtain the desired reliability by N iterative corrections in the worst case, the data read from the disk must have at least N + 2 blocks to secure the desired reliability. Will be.

FIG. 2 is a schematic diagram of an SRAM memory according to the present invention, in which the horizontal direction represents the time axis and the vertical direction represents the RAM address. In the case of n times of repeated corrections during the processing time, error correction is performed during the n-block processing period, data transmission is performed during the one-block processing period, and data buffering is performed during the one-block processing period.

That is, when performing error correction of data consisting of blocks, if there are N blocks, error correction is performed in N error correction blocks, one block transfers data, and one block processes data buffering within a given address.

FIG. 4 is a detailed view of the digital signal processor 4 of FIG. 1, as shown therein, descrambling 6 for descrambling to receive serial input data, a synchronous detector 7 for sensing a synchronous signal, A clock and timing generator 8 for generating a clock signal, a header / sub header register 9 for storing header and subheader values, n error correction blocks 10 for correcting errors, and repetitive error correction Generates a recurring error correction check circuit 13 for checking for presence, a CRC register 14 for storing a circuit redundancy check value, a write address 15, an error correction check and an error detection check signal. An error correction check (ELL) and an error detection check (EDC) register 16, a direct memory access controller 17 that controls direct memory access (DMA), a command register 18, and a bus adapter 19).

Referring to the data processing method of the present invention configured as described above in detail.

The host central processing unit 1 outputs the location and amount of data where desired data is stored through the host adapter 2 to an optical disk drive. Therefore, the microcomputer 5 performs data acquisition using the information obtained by the above functions.

First, data is obtained by using light from the disk. If the microcomputer 5 checks whether the data is data of a desired address and determines that the data is of a desired address, the data is transferred to the SRAM through the digital signal processor 4. It is written in (3), which is called data buffering.

As such, the data inputted to the SRAM 3 requires a process of correctly processing a portion where an error occurs due to various reasons.

When it is determined that the error has been sufficiently eliminated, the data is read from the SRAM 3 and sent to the host CPU 1 through the host adapter 2, which is called transferring.

In this process, Oth on the horizontal axis of FIG. 2 represents the time of buffering the 0 block, and when decoding is necessary n times for a given block, it becomes the decoding time from the 1th block to the nth block. (Between 0 and 1 of address axis)

It should not be greater than the buffering time at least on the time base.

In addition, when the block size is K, the size of the SRAM 3 can reproduce data having a desired reliability when (N + 2) x K or more.

If the size of the SRAM 3 is smaller than (N + 2) × K, the buffering area and the transferring area cannot be reduced, and thus the decoding area is reduced, so that iterative correction of N times cannot be performed, thus failing to have the desired reliability. The block will come out.

3 is a flowchart of the present invention, when a command is first issued from the host to the optical drive system, the microcomputer interprets the command and finds a desired address on the disk.

In this process, the motor control is driven to perform track jump and so on, and the desired address is found. Once the address is found, the data of the part is read. In case of decoding and error correction, one block of data is read from the given address and written to SRAM, and the decoder and interrupt are checked by the microprocessor. The data written to SRAM is read again to confirm that the decoding process is completed.

When the decoding process is finished, this data is sent to the host. The decoding process will be described in detail with reference to FIG. If the desired address is found by reading the header register value, data must be reproduced and sent to the host from there, so the data is first written to SRAM, and the recorded data is read again and decoded.

When decoding is performed in this way, it is checked whether error correction is correctly performed on the block, which is performed by the repetitive error correction check circuit 13. This is a generating polynomial defined in GF (2 ⁸ ) after completion of the correction, and receives the data of the given block 22 and checks whether the value is 0 to check for repeat error correction. If iterative correction is necessary here, the error correction is performed again in the second correction circuit with the value once corrected. When the correction circuit is activated at the second time, the first error correction circuit reads the block data written to the RAM and corrects the error.

As described above, the present invention can realize the speed and accuracy essential for the memory device of a computer by reproducing data having a desired reliability in a short time.

That is, in the case of data used in the memory system for error correction of data, one-byte errors can be fatal to their contents, so accurate data is required as much as possible. However, there is a case where error correction is unsatisfactory for one error correction in an actual decoding system. In such a case, iterative error correction according to the present invention has the effect of accurately correcting the error within a short time without time delay.

Claims (1)

A data processing method in an optical storage device that reads data on an optical information disk, decodes the data, and delivers the same to a host system, the method comprising: searching for data written on the disk, and a desired address data block in the searching step If it is detected by the microcomputer to detect the address data in the SRAM through the digital signal processor, the step of repeatedly correcting the address data desired number of times, and after the iterative correction step stored in the SRAM And transmitting data to a host.

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