KR940005870Y1 - Multi input detecting device - Google Patents

Abstract

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Description

Multiple input detector

1 is a conventional two-input detection device.

2 is a two-input detection device according to the present invention.

3 is an N-input detection device according to the present invention.

4 is an operation state table of the two-input detection device according to the present invention.

* Explanation of symbols for main parts of the drawings

Inv, Inv ': Inverter A ₁ -A ₄ : End gate

OR: Oagate P ₁ -P _n : P Mos

Rx, Regv, R ₁ -R _n : Resistor C ₀ -C5 _n : Comparator

N ₁ -N _n : Node Q ₀ -Q _n : Output

V _N1 -N _Nn : Voltage at each node Cs: A / D converter

Rds ₁ -RdS _n : Internal resistance of PMOS

The present invention relates to a multi-input detection device, and more particularly, to a multi-input detection device that detects a low level or a high level in a multi-input and is suitable for multi-input counting.

In the prior art configuration, as shown in FIG. 1, the input "A" is input to one end of the end gates A ₁ and A _{2 and is} connected to one end of the end gates A ₃ and A ₄ through the inverter I ₂ . The input "B" is input to the other terminals of the AND gates A ₁ and A ₃ , and is input to the other terminals of the AND gates A ₂ and A ₄ through the inverter I ₁ , and the AND gate ( A ₁ ) is output (Q ₂ ), the output of the AND gate (A ₂ , A ₃ ) is output (Q ₁ ) through the oragate (OR), the output (Q ₀ ) through the AND gate (A ₄ ) Looking at the operating state of the circuit configuration to the configuration as follows.

In FIG. 1, if the inputs A and B are all low level, the input of the AND gate A ₁ is low level, so the output Q ₂ is low level, and the input of the AND gate A ₂ is low level. Since the high level and the inputs of the AND gate A ₃ are high level and low level, the inputs of the OR gate OR are all low level, and the output Q ₁ is low level, and the input of the AND gate A ₄ is low. Are all at high level, so output Q ₀ is at high level.

With this logic, if the inputs (A, B) are all at the high level, the output (Q ₂ ) is at the high level, and the remaining outputs (Q ₀ , Q ₁ ) are at the low level, and the input (A) is at the high level, the input ( When B) is low level, the output of the AND gate A ₂ becomes high level, and the output Q ₁ becomes high level, when the input A is low level and the input B is high level, The output of A ₃ ) becomes high level and the output Q ₁ becomes high level.

In the conventional technology described above, if the number of inputs is two, four AND gates (A ₁ -A ₄ ), one OA gate (OR), and two inverters (I ₁ , I ₂ ) are required. If the number of inputs is 3, the gates are 9 endgates, 2 oragates, and 3 inverters, and 14 are all required.When the inputs are 4, 16 endgates, 3 oragates, and 4 inverters are used. You will need a gate.

That is, if the number of inputs is N, the number of gates required for this is n = N ² + 2N-1. Therefore, as the number of inputs increases, the number of gates required increases exponentially.

Accordingly, the circuit configuration of the present invention to improve the above problems will be described according to the accompanying drawings.

2 shows a two-input detection apparatus according to the present invention. Looking at the connection configuration thereof, _two PMOSs (P ₁ and P ₂ ) are connected in parallel to one side of the power supply (V _DD ) and the other side of the resistor ( Grounded through Rx), the inputs (A, B) are connected to the gates through inverters (Inv, Inv '), and "+" of each of the three comparators (C ₁ -C ₃ ) at node N ₁ on the ground side. The "terminal" is connected, and the "-" terminals of each of the three comparators C ₁ -C ₃ are connected to a reference voltage having a constant difference by the number of resistors Regv, R ₂ and R ₄ .

The resistors (Regv, R ₂ , R ₄ ) are connected in series between the power supply (V _DD ) and ground, so that the power supply (V _DD2 ) is connected through the resistor (Regv) to the "-" terminal of the comparator (C ₁ ). C ₂₎ of the "-" terminal is connected through a power supply (V _DD2) the resistance (Regv) and a resistor (R _2), a comparator (C ₃₎ of the "-" terminal of the power supply (V _DD2) the resistance (Regv , R ₂ , R ₄ ).

Referring to the operation state and the effect of the two-input detection device of the present invention as follows.

According to the inputs A and B in FIG. 2, the current I has three values.

That is, when the inputs A and B are both at high level, a low level is applied to the gates of the P-MOSs P ₁ and P ₂ through the inverters Inv and Inv ', so that the P-MOSs P ₁ and P ₂ Since the current I is set to "Imax" because both are not operated and the inputs A and B are all at the low level, since the P-MOSs P ₁ and P ₂ are not operated at all, the current I is "0". When one of (A, B) is high level, the other is low level, only one of the PMOS (P ₁ , P ₂ ) is conducting and the current (I) is " Where the three types of currents (0, , Imax) divided by " Imax " yields " 0, ½, 1 " (see FIG. 4A).

"Imax" is input (A, B) are both generated when the high level, and wherein P MOS (P _1, P ₂₎ will have the same characteristics, and if the internal resistance is referred to "Rds", a voltage source (V _DD) and the node Since resistance (Ry) between (N ₁ ) is PMOS (P ₁ , P ₂ ) is parallel connection, increasing resistance (Ry) is PMOS (P ₁ , P ₂ ) is parallel connection, so increasing resistance (Ry) is " "Becomes.

If the resistance Ry is much larger than the resistance Rx, "And the zone (V _N1 ) over node (N ₁ ) is" "to be.

If the input is high level in this way, current (I) is " And the voltage V _N1 at node N ₁ at this time is " "to be.

In this way, if only one input is high level, current (I) is " And the voltage V _N1 at node N ₁ at this time is " "to be.

If the inputs A and B are both at low level, the PMOS P ₁ and P ₂ do not operate, so the voltage across the node N ₁ becomes "0 [V]" (see also FIG. 4b).

Next, the A / D converter Cs will be described. The resistor Regv is equal to the resistor Ry, and the resistor Therefore, the voltage across node (N ₂ ) (V _N2 ) And the voltage across node N ₃ (V _N3 ) is " The voltage applied to the node N ₄ becomes 0 [V] (see also FIG. 4b), and the comparators C ₁ -C ₃ have a high level voltage if the voltages coming into the terminal (+) and the terminal (-) are the same. Export

The input terminal (-) of the comparator C ₁ has a voltage V _N2 , that is, Is applied to the input terminal (-) of the comparator (C ₂ ), that is, the voltage (V _N3 ), Is applied, and "0 [V]" is applied to the input terminal (-) of the comparator C ₃ .

Since the voltage V _N1 is applied to the input terminals + of the comparators C ₁ -C ₃ , the voltage V _N1 is changed to the same state as the voltage V _{N1 of} FIG. 4b.

Therefore, as shown in FIG. 4B, if the inputs A and B are all at the low level, the outputs Q ₀ are at the high level because the inputs V _N1 and V _N4 of the comparator C ₃ are equal to each other as 0 [V]. If this is the only one type of high level (V _N1, V _N3), the input (V _N1, V _N3) of the comparator (C ₂₎ to each other Since the output Q ₁ is at the high level, and the inputs A and B are at the high level, the inputs V _N1 and V _N2 of the comparator C ₁ are different from each other. As a result, the output Q ₂ is at a high level (see also 4c).

If there are many inputs in this way, as shown in FIG. 3, PMOS (P ₁ , P _n ) as many as the number of inputs are connected in parallel according to the number of inputs, and each PMOS (P ₁ -P _n ) The input signal is applied to the gate to connect a resistor (Rds ₁ // Rds ₂ //… Rds _n ") synthesized with an internal resistance (Rds) and a resistor (Regv), which is an equivalent resistance (Ry), and outputs a resistor (Rx). The same resistance (R ₁ -R ₇ ) divided by the number of (Q ₀ -Q ₇ ) can be connected between the input terminals (-) of each comparator (C ₀ -C _n ).

Therefore, the multi-input detection device according to the present invention is a multi-input device by increasing one PMOS, inverter, comparator, and resistance according to the input increase without increasing the exponential logic element according to the increase of the input as described above. It will have the effect that can be configured.

Claims (1)

N PMOSs having their gates as their respective input terminals are connected in parallel to a power supply (V _DD ) terminal, the nodes N ₁ of each PMOS are commonly grounded through a resistor, and the common node N _{1 is connected.} ) Is commonly connected to the non-inverting terminal (+) of n + 1 comparators (C _n -C ₀ ), and a reference voltage having a constant difference is connected to the inverting terminal (-) of the comparator (C _n -C ₀ ). Detecting the number of inputs by the output level of each comparator (C _n -C ₀ ).