KR940004815A

KR940004815A - Semiconductor device and manufacturing method thereof

Info

Publication number: KR940004815A
Application number: KR1019920015590A
Authority: KR
Inventors: 김윤기
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1992-08-28
Filing date: 1992-08-28
Publication date: 1994-03-16
Also published as: KR100269275B1

Abstract

본 발명에 의하면 반도체기판, 상기 반도체기판에 형성되고 소자활성 영역을 한정하는 소자분리영역, 상기 소자활성영역 및 소자분리영역상에 형성된 워드라인, 상기 활성영역의 소오스영역에 형성되고, 소오스영역상에 형성된 캐패시터와 소오스영역과의 전기적 접촉을 위한 2개의 캐패시터전극 접촉구 및 상기 활성영역의 중앙부에 형성되고, 활성영역상의 비트라인과 드레인영역과의 전기적 접촉을 위한 비트라인 접촉구를 포함하는 반도체장치에서, 하나의 활성영역에 형성되는 상기 2개의 캐패시터전극 접촉구 및 상기 비트라인 접촉구는 비선형상으로 형성된 반도체장치 및 그의 제조방법이 제공된다. 비트라인 접촉구와 캐패시터전극 접촉구를 비선형으로 형성함으로써, 셀내의 불용면적을 활성영역으로 활용할 수 있고, 폴리실리콘을 사용하여, 상기 접촉구를 매립할 수 있으며, 고집적화된 반도체장치의 제조에 트렌치 매립방법에 의한 소자분리영역의 형성이 효율적이다.According to the present invention, a semiconductor substrate, an element isolation region formed on the semiconductor substrate and defining an element active region, a word line formed on the element active region and an element isolation region, and formed on a source region of the active region, A semiconductor including two capacitor electrode contact holes for electrical contact between a capacitor and a source region formed in the center, and a bit line contact hole formed at a central portion of the active region and for electrically contacting a bit line and a drain region on the active region; In the apparatus, a semiconductor device and a manufacturing method thereof are provided in which the two capacitor electrode contacts and the bit line contacts are formed in a non-linear shape in one active region. By forming the bit line contact and the capacitor electrode contact in a non-linear manner, the insoluble area in the cell can be utilized as an active region, and the contact can be buried using polysilicon, and the trench is embedded in the fabrication of highly integrated semiconductor devices. Formation of the device isolation region by the method is efficient.

Description

Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 DRAM 셀의 레이아우트를 도시한 것이다.5 shows a layout of a DRAM cell of the present invention.

제6도는 상기 제5도의 AA′선을 절단한 단면도를 나타낸 것이고,6 is a cross-sectional view taken along line AA ′ of FIG. 5.

제7도는 상기 제5도의 BB′선을 절단한 단면도를 나타낸 것이고,FIG. 7 is a cross-sectional view taken along line BB ′ of FIG. 5.

제8도는 상기 제5도의 CC′선을 절단한 단면도를 나타낸 것이다.FIG. 8 is a cross-sectional view taken along line CC ′ of FIG. 5.

Claims

A semiconductor substrate, a device isolation region formed on the semiconductor substrate and defining a device active region, a word line formed on the device active region and the device isolation region, a capacitor formed on a source region of the active region, and a capacitor formed on the source region; In a semiconductor device comprising two capacitor electrode contacts for electrical contact with a source region and a central portion of the active region, and a bitline contact for electrical contact between the bit line and the drain region on the active region, one of Wherein the two capacitor electrode contacts and the bit line contacts are formed in a non-linear shape in the active region of the semiconductor device.

The semiconductor device according to claim 1, wherein the active region has a T-shape, and the isolation region comprises a trench and an insulating material filling the trench.

The semiconductor device according to claim 1, wherein the bit line contact hole and the capacitor electrode contact hole are filled with polysilicon doped with impurities.

The semiconductor device according to claim 1, wherein the width of the device isolation region is constant over the entire surface of the semiconductor substrate.

Forming a trench in a semiconductor substrate and embedding it with an insulating material to form a device isolation region defining a T-shaped active region, wherein a capacitor electrode contact and a bit line contact are non-linear to each other on the T-shaped active region A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor device.