KR940004711A - Polysilicon Layer Formation Method - Google Patents
Polysilicon Layer Formation Method Download PDFInfo
- Publication number
- KR940004711A KR940004711A KR1019920015521A KR920015521A KR940004711A KR 940004711 A KR940004711 A KR 940004711A KR 1019920015521 A KR1019920015521 A KR 1019920015521A KR 920015521 A KR920015521 A KR 920015521A KR 940004711 A KR940004711 A KR 940004711A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon layer
- type impurity
- layer
- ion
- amorphous silicon
- Prior art date
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 고집적 반도체 소자의 폴리실리콘층 형성방법에 관한것으로 폴리실리콘층을 1000Å이하의 두께로 형성하고, 그 하부에 있는 게이트 산화막의 특성을 보존하기 위하여, 실리콘 기판 상부에 게이트 산화막과 얇은막의 폴리실리콘층을 적층하는 단계와, 폴리실리콘층 상부에서 질량이 큰 n형 불순물을 이온주입하여 폴리실리콘층 상부면의 일정두께를 아몰포스화된 실리콘층을 형성하는 단계와, 아몰포스화된 실리콘층 상부에서 일반적인 n형 불순물을 이온주입하는 단계로 이루어지는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polysilicon layer of a highly integrated semiconductor device, wherein the polysilicon layer is formed to a thickness of 1000 Å or less, and in order to preserve the characteristics of the gate oxide layer under the polysilicon layer, Laminating a silicon layer, ion-implanting a large n-type impurity on the polysilicon layer to form an amorphous silicon layer having a predetermined thickness of the upper surface of the polysilicon layer, and an amorphous silicon layer It is a technique consisting of ion implantation of the common n-type impurities in the upper portion.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2A도 내지 제2C도는 본 발명에 의해 n형 불순물이 도포된 폴리실리콘 박막 형성단계를 도시한 단면도.2A to 2C are cross-sectional views showing a polysilicon thin film forming step to which n-type impurities are applied according to the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920015521A KR940004711A (en) | 1992-08-28 | 1992-08-28 | Polysilicon Layer Formation Method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920015521A KR940004711A (en) | 1992-08-28 | 1992-08-28 | Polysilicon Layer Formation Method |
Publications (1)
Publication Number | Publication Date |
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KR940004711A true KR940004711A (en) | 1994-03-15 |
Family
ID=67147911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920015521A KR940004711A (en) | 1992-08-28 | 1992-08-28 | Polysilicon Layer Formation Method |
Country Status (1)
Country | Link |
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KR (1) | KR940004711A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100386616B1 (en) * | 2000-12-04 | 2003-06-02 | 주식회사 하이닉스반도체 | Method for forming fine structure poly film |
KR100475895B1 (en) * | 1997-12-30 | 2005-06-17 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
-
1992
- 1992-08-28 KR KR1019920015521A patent/KR940004711A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100475895B1 (en) * | 1997-12-30 | 2005-06-17 | 주식회사 하이닉스반도체 | Semiconductor device manufacturing method |
KR100386616B1 (en) * | 2000-12-04 | 2003-06-02 | 주식회사 하이닉스반도체 | Method for forming fine structure poly film |
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