KR940004479B1 - Dynamic equalizing control circuit for magnetic recording device - Google Patents
Dynamic equalizing control circuit for magnetic recording device Download PDFInfo
- Publication number
- KR940004479B1 KR940004479B1 KR1019910021136A KR910021136A KR940004479B1 KR 940004479 B1 KR940004479 B1 KR 940004479B1 KR 1019910021136 A KR1019910021136 A KR 1019910021136A KR 910021136 A KR910021136 A KR 910021136A KR 940004479 B1 KR940004479 B1 KR 940004479B1
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- KR
- South Korea
- Prior art keywords
- magnetic recording
- control circuit
- signal
- recording device
- boost
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/127—Structure or manufacture of heads, e.g. inductive
- G11B5/33—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only
- G11B5/35—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only having vibrating elements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.
제3도는 디스크 영역을 나타낸 도면.3 shows a disk area.
제4도는 데이타의 밀도에 따른 데이타 영역별 데이타 펄스 파형도.4 is a data pulse waveform diagram of data regions according to data density.
제5도는 본 발명에 따른 고립 신호상에서의 등화 효과 특성도.5 is an equalization effect characteristic diagram on an isolated signal according to the present invention.
본 발명은 자기 기록장치에 있어서 등화 제어회로에 관한 것으로, 특히 트랙정보로부터 등화량을 데이타 영역마다 조절하여 상기 각 트랙마다 크기가 달라짐으로 인한 인접 비트간의 상호 간섭에 의한 피이크 쉬프트(Peak Shift)를 최소화시킬 수 있는 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalization control circuit in a magnetic recording apparatus. In particular, a peak shift due to mutual interference between adjacent bits due to a change in size for each track is adjusted by adjusting the amount of equalization from track information to each data area. It relates to a circuit that can be minimized.
헤드로부터 받은 로우신호(raw-signal)를 펄스 감지기(101)에 의해 증폭되어 외부 필터(102)를 거쳐 등화 및 필터링이 행해진다. 이때 입력신호는 헤드의 디스크상의 위치에 관계없이 일정한 부우스트(Boost)양으로 등화되어 펄스감지를 위한 미분기로 피이딩된다. 결국 피이딩된 신호는 여러 과정을 거쳐 엔코딩되는 리드 데이타단를 출력한다.The raw signal received from the head is amplified by the pulse detector 101 and equalized and filtered through the external filter 102. At this time, the input signal is equalized to a constant boost amount regardless of the position of the head on the disk and fed to the differential for pulse detection. Eventually, the fed signal is read data stage encoded through various processes. Outputs
일반적으로 디스크 영역은 제3도와 같이 나누어지는데, 실제 헤드가 데이타를 읽을 경우, 디스크에 쓰여진 데이타는 밀도가 제4도와 같이 서로 다른 영역에서 존재하게 된다. 이때 안쪽(Inner)이나 바깥쪽(Outer)에 같은 수의 데이타가 있음에도 불구하고 밀도가 다르고 진폭이 틀린데 종래 기술은 모든 존(Zone)에 대해 등화를 동일한 부우스트 양으로 함으로써 상호간의 간섭에 의해 제4도(4B)와 같이 피이크쉬프팅이 되어 이에 능동적으로 대처하지 못하며, 이것은 고기록 밀도의 디스크 드라이브에 적합하지 않게되는 문제점이 있었다.Generally, the disk area is divided as shown in FIG. 3, and when the actual head reads the data, the data written on the disk is present in different areas as shown in FIG. At this time, although there is the same number of data in the inner or outer, the density and the amplitude are different, but the prior art has the same boosting amount for all zones. As shown in FIG. 4B, the peak shifting is not actively handled, which is not suitable for a high write density disk drive.
따라서 본 발명의 목적은 자기 기록장치에 있어서 전송레이트를 개선시키고, 미분기 출력의 S/N비 특성을 향상시키며, 리드 신호를 슬리밍(Slimming)함으로써 상호 간섭에 의해 야기되는 피이크 쉬프팅을 줄일 수 있는 회로를 제공함에 있다.Therefore, an object of the present invention is to improve the transmission rate, improve the S / N ratio characteristics of the differentiator output in the magnetic recording apparatus, and reduce the peak shift caused by mutual interference by slimming the read signal. In providing.
이하 본 발명을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 회로도로서, 헤드와 연결되어 디스크로부터 센싱되는 신호를 입력단(Rx, Ry)을 통해 펄스감지기(201)에서 감지하여 능동필터(202)에서 필터링하여 콘트롤러의 리드 제어단으로 출력토록 구성되어 있으며, 상기 능동필터(202)의 등화용 부우스트 양조절단(VBP)에 디지탈/아나로그 변환기(203)의 출력단(Vout)에 연결되고 상기 디지탈/아나로그 변환기(203)의 입력단에 중앙처리장치(CPU)(204)의 출력단에 연결되며, 상기 디지탈/아나로그 변환기(203)의 출력단(Vout)과 상기 능동필터(202)의 부우스트 양조절단(VBP)의 연결라인에 저항(Rext1, Rext2)을 통해 입력을 풀업(Full up)하도록 되어 있다.2 is a circuit diagram according to the present invention, in which the signal sensed from the disk connected to the head is sensed by the pulse detector 201 through the input terminals Rx and Ry and filtered by the active filter 202 to control the lead control of the controller. It is configured to output, and is connected to the output (Vout) of the digital / analog converter 203 to the boost boost amount control stage (V BP ) of the active filter 202 and the digital / analog converter 203 It is connected to the output terminal of the central processing unit (CPU) 204, the input terminal of the output terminal (Vout) of the digital / analog converter 203 and the boost boost control terminal (V BP ) of the active filter 202 The inputs are pulled up through the resistors Rext1 and Rext2.
제3도와 같이 디스크상의 데이타를 리드할 시 HDD는 먼저 리드해야 할 트랙을 먼저 찾아야 한다. 이때 CPU(204)는 트랙의 위치를 디지탈/아나로그 변환기(203)(Digital-to-Analog Converter)로 입력되어 펄스 감지기(201)의 외부 필터인 능동필터(203)의 조절단(VBP)를 가변시킴으로써 부우스트양(Equalization)의 값을 변경하게 된다(VR : 고정된 상수).When reading data on a disc as shown in FIG. 3, the HDD must first find a track to be read first. At this time, the CPU 204 inputs the position of the track to the digital-to-analog converter 203 and adjusts the control stage V BP of the active filter 203 which is an external filter of the pulse detector 201. Equalization by varying Will change the value of (VR: fixed constant).
따라서 부우스트되는 양이 디스크상의 각 트랙마다 그 크기가 자동적으로 달라짐으로써 인접비트간의 상호 간섭에 의한 피이크 쉬프트를 최소화한다.Therefore, the amount of boost is automatically changed in size for each track on the disk, thereby minimizing the peak shift due to mutual interference between adjacent bits.
제4도에서 볼 수 있듯이 신호의 상호 간섭에 의해 피이크 쉬프트가 줄어듬을 알 수 있다.As can be seen in FIG. 4, the peak shift is reduced by mutual interference of signals.
상기 부우스트양 FB(dB)의 계산은 하기식과 같다.The calculation of the boost amount FB (dB) is as follows.
FB(dB)=20log[K VBP+1]FB (dB) = 20log [KV BP +1]
K : 부우스트 상수이고, 제2도에서 저항(Rext1, Rext2)은 능동필터(202)의 조절단(VBP) 입력 조건을 위한 외부 저항이다.K is the boost constant, and in FIG. 2 the resistors Rext1 and Rext2 are external resistors for the control stage V BP input conditions of the active filter 202.
그리고 디지탈/아나로그 변환기(202)는 중앙처리장치(204)로부터 헤드의 위치 즉 리드(Read)해야 할 트랙을 계산하여 전압으로 바꾸면 상기 바꾸어진 전압이 바로 VBP임으로 부우스트 양이 조절됨으로써 리드시 각 트랙마다 알맞은 부우스트 양으로 리드된다.And digital / analog converter 202 leads the change is arbitrarily just V BP Buu host amount control voltage being thereby changing the voltage to calculate the track to the location that is read (Read) of the head from the central processing unit (204) Each track leads to the correct amount of boost.
이때 VBP와 디지탈/아나로그 변환기(203)의 출력단(Vout)사이에 연결되는 저항(Rext1)과 (Rext2)는 [0<(VBP)<2.2V, 즉 0<VBP=Vout(2n)<2.2]VBP입력 조건을 만족하기 위해 출력신호에 대해 풀업시킨다.At this time, the resistors Rext1 and Rext2 connected between the VBP and the output terminal Vout of the digital / analog converter 203 are [0 <(VBP) <2.2V, that is, 0 <V BP = Vout (2 n ). <2.2] V BP Pulls up the output signal to satisfy the input condition.
상술한 바와 같이 리드신호의 부우스트양을 헤드의 위치에 따라 항상 가변됨으로써 최적의 리드 신호를 리드백(readback)할 수 있으며, 이에 따라 고정도의 리드 기술을 사용함으로써 고기록 디스크 드라이브의 데이타 안전성을 기여할 수 있는 이점이 있다.As described above, since the amount of boost of the read signal is always varied according to the position of the head, the optimum read signal can be readback. Therefore, the data read of the high-record disk drive can be improved by using a high-precision read technology. There is an advantage to contribute.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910021136A KR940004479B1 (en) | 1991-11-25 | 1991-11-25 | Dynamic equalizing control circuit for magnetic recording device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910021136A KR940004479B1 (en) | 1991-11-25 | 1991-11-25 | Dynamic equalizing control circuit for magnetic recording device |
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| Publication Number | Publication Date |
|---|---|
| KR930010871A KR930010871A (en) | 1993-06-23 |
| KR940004479B1 true KR940004479B1 (en) | 1994-05-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910021136A KR940004479B1 (en) | 1991-11-25 | 1991-11-25 | Dynamic equalizing control circuit for magnetic recording device |
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| KR (1) | KR940004479B1 (en) |
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1991
- 1991-11-25 KR KR1019910021136A patent/KR940004479B1/en not_active IP Right Cessation
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| KR930010871A (en) | 1993-06-23 |
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