KR940003509Y1 - Catv input circuit - Google Patents
Catv input circuit Download PDFInfo
- Publication number
- KR940003509Y1 KR940003509Y1 KR2019880014316U KR880014316U KR940003509Y1 KR 940003509 Y1 KR940003509 Y1 KR 940003509Y1 KR 2019880014316 U KR2019880014316 U KR 2019880014316U KR 880014316 U KR880014316 U KR 880014316U KR 940003509 Y1 KR940003509 Y1 KR 940003509Y1
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- KR
- South Korea
- Prior art keywords
- trap
- adjacent
- input
- circuit
- input circuit
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/50—Tuning indicators; Automatic tuning control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/10—Adaptations for transmission by electrical cable
- H04N7/102—Circuits therefor, e.g. noise reducers, equalisers, amplifiers
Abstract
내용 없음.No content.
Description
제1도는 본 고안과 관련된 유선 TV수신기의 부분 개략도.1 is a partial schematic view of a cable TV receiver according to the present invention.
제2도는 제1도의 안테나측에서의 주파수 스펙트럼 참고도.2 is a frequency spectrum reference diagram at the antenna side of FIG.
제3도는 제1도의 입력동조부측에서의 신호특성 참고도.3 is a signal characteristic reference diagram at the input tuning unit side of FIG.
제4도는 본 고안에 의한 회로도.4 is a circuit diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 인접채널트랩부 11 : 저역인접트랩회로1: Adjacent Channel Trap Section 11: Low Pass Adjacent Trap Circuit
12 : 고역인저트랩회로 VT: 튜닝전압단12: High frequency insulator trap circuit V T : Tuning voltage terminal
본 고안은 유선 TV수신기의 입력회로와 관련된 것으로서, 이는 특히 상기 입력회로에 수신채널의 인접채널에 대한 가변 동조트랩회로를 마련하여 화상에서의 비트발생을 양호히 제거하려는 입력회로에 관한 것이다.The present invention relates to an input circuit of a wired TV receiver, and more particularly, to an input circuit that provides a variable tuning trap circuit for an adjacent channel of a receiving channel in the input circuit so as to eliminate bit generation in an image well.
근자에는 유선 TV방송이 성행해짐에 따라 TV수상기등의 신호입력단말에 여러가지 신호가 유사한 신호세력을 가지고 입력되는 경우가 빈번하다.In recent years, as wired TV broadcasting becomes popular, various signals are frequently inputted with similar signal forces to signal input terminals such as TV receivers.
일예로, 유선 TV 방송국의 갯수가 증가됨에 의해 여러개의 방송국신호가 TV수상기등의 안테나측에 같은 세기(70㏈-80㏈ 정도)를 가지고 입력된다.For example, as the number of cable TV broadcast stations is increased, a plurality of broadcast station signals are input to the antenna side of the TV receiver and the like with the same intensity (about 70 Hz to 80 Hz).
그러므로 이들 신호와 신호간의 상호간섭이나 비트문제가 상당히 대두되어 있으며 특히 인접채널에 대한 방해배재능력이 요구되어지고 있다.Therefore, mutual interference or bit problems between these signals and signals have been raised considerably, and in particular, the ability to suppress interference on adjacent channels is required.
즉, 제1도에서는 TV수신기측의 안테나(2)와 고역여파기(3), 입력동조부(4), RF증폭단(5)까지의 입력회로를 나타내고 있다.That is, Fig. 1 shows the input circuits up to the antenna 2, the high frequency filter 3, the input tuning section 4, and the RF amplifier stage 5 on the TV receiver side.
그리고, 상기 안테나(2)측에는 제2도와 같이 같온 세기의 주파수 스펙트럼이 나타날수 있다.And, the frequency spectrum of the same intensity may appear on the antenna 2 side as shown in FIG.
여기서 f0-f1, f2-f1,‥‥‥f5-f4는 각기 6㎒(또는 7㎒, 8㎒) 범위라 가정한다.It is assumed here that f 0 -f 1 , f 2 -f 1 ,..., F 5 -f 4 are in the range of 6 MHz (or 7 MHz, 8 MHz), respectively.
이러한 안테나(2)측의 신호스펙트럼은 입력동조부(4)를 거쳐 특정채널 RF증폭단(5)으로 보내게 되며, 이때의 파형은 제3도와 같이 나타내었다.The signal spectrum of the antenna 2 side is sent to the specific channel RF amplifier stage 5 through the input tuning section 4, and the waveform at this time is shown in FIG.
여기서는 그 대역폭이 20-30㎒에 상당하고 특정주파수를 fd라 가정할때 그 인접채널주파수 f1, f2와는 그 주파수 세기의 차이가 별로 크지 않음을 알수 있다.Here, when the bandwidth corresponds to 20-30MHz and a certain frequency is fd, it can be seen that the difference in frequency strength is not very large from that of the adjacent channel frequencies f 1 and f 2 .
따라서, 특정주파수 fd에 디한 인접패널주파수의 영향으로 이들이 화상의 비트현상을 야기케되므로서 좀더 양호한 TV수상기의 입력특성을 기대할수 없는 것이었다.Therefore, it is impossible to expect better input characteristics of a TV receiver because they cause bit phenomena of the image due to the influence of adjacent panel frequencies at a specific frequency fd.
본 고안은 상기와 같은 종래의 단점을 개선하고져 안출한 것이다.The present invention has been made to improve the above-mentioned disadvantages.
본 고안은 특히 상기 입력회로가 특정채널에의인 인접채널대역만을 가변적으로 트랩하도록 하는 입력회로도 되어 그 인접채널에 의한 신호방해현상을 제거하도록한 것이다.In particular, the present invention is also an input circuit that allows the input circuit to trap only the adjacent channel bands to a specific channel to eliminate the signal disturbance caused by the adjacent channel.
이하에서 이를 좀더 상세히 설명하면 다음과 같다.This will be described in more detail below.
즉, 제4도는 본 고안에 의한 인접채널트랩부(1)가 구비된 입력회로를 나타내었다.That is, FIG. 4 shows an input circuit provided with the adjacent channel trap section 1 according to the present invention.
여기서는 안테나(2)가 연결된 고역여파기(3)와 입력동조부(4) 사이에 인접채널트랩부(1)가 연결되어지고, 상기 인접채널트랩부(1)는 저역인접트랙회로(11)와 고역인접트랩회로(12)가 튜닝전압단(VT)에 공통으로 이어진 구성으로 된다.Here, the adjacent channel trap unit 1 is connected between the high frequency filter 3 and the input tuning unit 4 to which the antenna 2 is connected, and the adjacent channel trap unit 1 is connected to the low-pass adjacent track circuit 11. The high frequency adjacent trap circuit 12 is configured to be connected to the tuning voltage terminal V T in common.
또, 상기 저역 및 고역 인접트랩회로(11,12)는 트랩코일(L1,L2), 트랩캐패시 터(C1,C2), 바렉터다이오드(D1,D2)에 의한 특정주파수 트랩회로로 된다.In addition, the low- and high-pass adjacent trap circuits 11 and 12 are specified by trap coils L 1 and L 2 , trap capacitors C 1 and C 2 , and varactor diodes D 1 and D 2 . It becomes a frequency trap circuit.
이러한 구성의 본 고안은 전자튜닝회로등에 의해 특정채널주파수가 선택될때는 튜닝전압(VT)이 인가되어 저역 및 고역인접트랩회로(11,12)의 바렉터다이오드(D1,D2)에 소정전압이 가해진다.According to the present invention of the above configuration, when a specific channel frequency is selected by an electronic tuning circuit or the like, a tuning voltage V T is applied to the selector diodes D 1 and D 2 of the low and high pass adjacent trap circuits 11 and 12. A predetermined voltage is applied.
이에의해 상기 특정주파수와의 인접채널에 대한 저역 및 고역부분에의 주파수는 상기 저역 및 고역인접트랩회로(11,12)로 제거되어지고 특정주파수만 입력동조부 (4)측으로 가해지는 것이다.Thus, the frequencies in the low and high ranges for the adjacent channel with the specific frequency are removed by the low and high adjacent trap circuits 11 and 12, and only the specific frequency is applied to the input tuning section 4 side.
또, 이때는 상기 특정 채널의 선국때마다 그 인접주파수의 트랩을 위한 가변전압이 발생하고 이를 튜닝전압단(VT)측으로 제공케되어진다.In this case, each time the channel is tuned, a variable voltage for trapping the adjacent frequency is generated and provided to the tuning voltage terminal V T.
이러한 본 고안은 유선 TV시스템에서 유선 TV수신기측의 입력회로에 특정채널외의 인접채널에 대한 가변주파수 트랩회로가 구비되어 이러한 회로에서의 인접채널에 대한 방해배제조건을 양호히 개설할수 있는 유익한 특징이 있는 것이다.The present invention has an advantageous feature that a variable frequency trap circuit for an adjacent channel other than a specific channel is provided in an input circuit of a cable TV receiver in a wired TV system, so that the interference rejection condition for the adjacent channel can be well established in such a circuit. will be.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880014316U KR940003509Y1 (en) | 1988-08-31 | 1988-08-31 | Catv input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880014316U KR940003509Y1 (en) | 1988-08-31 | 1988-08-31 | Catv input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900005966U KR900005966U (en) | 1990-03-09 |
| KR940003509Y1 true KR940003509Y1 (en) | 1994-05-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880014316U KR940003509Y1 (en) | 1988-08-31 | 1988-08-31 | Catv input circuit |
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| Country | Link |
|---|---|
| KR (1) | KR940003509Y1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100326889B1 (en) * | 1994-02-22 | 2002-07-22 | 월풀코포레이션 | Vertical axis washer |
-
1988
- 1988-08-31 KR KR2019880014316U patent/KR940003509Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100326889B1 (en) * | 1994-02-22 | 2002-07-22 | 월풀코포레이션 | Vertical axis washer |
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| Publication number | Publication date |
|---|---|
| KR900005966U (en) | 1990-03-09 |
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