KR940001549Y1 - Signal selected circuit - Google Patents

Abstract

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Description

Signal selection circuit

1 is a conventional signal selection (switching) circuit diagram.

2 is a circuit diagram showing an embodiment of a signal selection circuit according to the present invention.

3A to 3D are waveform diagrams of respective parts in FIG. 2.

* Explanation of symbols for main parts of the drawings

10: analog switch 20: buffer

30: selection control unit 40: mute circuit unit

50: Inverter C1 ~ C6 Capacitor

R1 to R7: Resistor Q1 to Q2: Transistor

The present invention relates to a signal switching circuit, and more particularly, to a circuit for reducing cross talk in a signal switching circuit for selectively inputting a plurality of input signals.

The signal switching circuit is a circuit for selecting and outputting only one input signal according to a selection control signal among a plurality of input signals. As shown in FIG. 1, the signal switching circuit is a signal output from the selection control unit 30 and one of two input signals. Refers to a circuit for outputting to the next stage such as the buffer 20.

At this time, in the switch unit 10, an unselected input signal is affected by the selected input signal, thereby causing crosstalk. Here, crosstalk refers to the leakage of arbitrary line signals to other lines through electrostatic or electronic coupling. In crosstalk, near-end crosstalk and crosstalk energy are opposite to the direction in which crosstalk energy is transmitted and the direction in which original signal energy is transmitted. There is a far-end crosstalk in the same direction in which the signal is transmitted and the direction in which the original signal energy is transmitted.

Normally, the crosstalk ratio is represented by the ratio of the crosstalk output voltage from the A channel appearing at the output terminal of the B channel to the signal voltage of the channel appearing at the output terminal of the A channel. Thus, in the conventional signal switching circuit, since the switch unit is controlled by the selection control signal to output the selected signal, crosstalk occurs due to switching, which affects the input signals.

That is, if the crosstalk characteristic of the analog switch is not good in the related art, when one input signal is selected, there is a problem that signals interfere with each other by the influence of the unselected signal.

In this regard, the present invention can solve the above problem by eliminating, that is, muting, a signal that is not selected according to the signal of the selection controller.

Accordingly, an object of the present invention is to provide a signal selection circuit that can suppress crosstalk occurring in the signal switching circuit.

Another object of the present invention is to provide a signal selection circuit that can implement a product having improved reliability since interference of signals is eliminated by suppressing crosstalk.

In order to achieve the above object, the present invention provides a signal selection circuit including switching means for selectively outputting one input signal among a plurality of input signals according to a selection control signal, wherein the selection control signal is generated to generate the selection control signal. A selection controller for controlling an operation; And a muting circuit unit for muting the input signals applied to the non-selected input terminals other than the input terminal selected according to the selection control signal.

Hereinafter, with reference to the accompanying drawings will be described in detail.

2 is a circuit diagram showing an embodiment of a signal selection circuit according to the present invention.

The input signal 1 and the input signal 2 are respectively input to a switching means for selecting one of two input signals via a capacitor C1 and a capacitor C2, for example, an analog switch 10, and the output of the analog switch 10 is It is input to the buffer 20 to be separated so as not to be affected by the front and rear ends.

In addition, the output of the selection controller 30 is input to the first mute circuit unit 41 for preventing crosstalk generated when one of the plurality of input signals is selected, and the inversion output of the selection controller 30 is one of a plurality of input signals. Input to the second mute circuit unit 42 to prevent crosstalk generated when selecting one, input signals passing through the capacitor (C1) and the capacitor (C2) is also input to the first, second mute circuit (41, 42) do.

Only one of the two inputs of the analog switch 10 is output to the next stage, and the first and second mute circuits 41 and 42 are configured to control input signals 1 and 2 passing through the capacitor C1 and the capacitor C2. For example, the ground GND is connected to the emitter terminal of the transistor Q1 and the transistor Q2. In addition, the resistor R2 and the capacitor C3 are connected in parallel between the base terminal and the ground of the transistor Q1, and the resistor R5 and the capacitor C4 are connected in parallel between the base terminal and the ground of the transistor Q2. It is connected.

On the other hand, the output signal of the selection control unit 30 is input to the contact point of the resistor R6 and the capacitor C6, at which time the other side of the capacitor C6 is connected to the ground. The signal passing through the resistor (R6) is divided into two again at the contact B, one end is input to the analog switch 10, the other end is passed through the resistor (R7) and divided into a capacitor (C5) connected to the contact C and ground. Lose. The contact C is divided into the resistor R4 and the inverter 50. One end passes through the resistor R4 and is coupled to the base end of the transistor Q2. The other end passes through the inverter 50 and the resistor R3. It is coupled to the base end of transistor Q1.

3A to 3D are waveform diagrams of the respective parts in FIG. 2, and FIG. 3A is an output signal (contact point A) of the selection controller 30, and FIG. 3B is a contact point B between the resistors R6 and R7. 3C shows a signal at the C junction between the resistor R4 and the inverter 50, and FIG. 3D shows an output signal (D contact) of the inverter 50, respectively.

Referring to the operation according to the configuration, first, one of the two input signals is implemented to select and output.

When the output voltage of the selection controller 30 is "low logic state (L) (a part of FIG. 3a), the analog switch 10 is connected to the upper end and the input signal 1 is output to the next buffer 20. do. At this time, since the signal at contact B (Figure 3b) is "L", the signal at contact C (Figure 3c) is also "L", and the signal at point D (Figure 3d) is "H" and the transistor ( Q1) is turned on and transistor Q2 is shut off. Therefore, the input signal 2 applied to the collector terminal of the transistor Q1 is bypassed to the ground via the transistor Q1. The capacitors C1 and C2 are for preventing high frequency noise, the resistors R2 and R5 are voltage drop resistors for conducting the transistors Q1 and Q2, and the capacitors C3, C4 and C6 are used for noise bypass. It became.

In addition, the resistor R7 and the electrolytic capacitor C5 constituting the integrating circuit protect the transistors Q1 and Q2 by delaying the signal for a predetermined time in order to prevent a transient phenomenon, and also chattering. It also serves to prevent.

Next, when the output voltage of the selection control unit 30 is in the "high logic state (H)" (b part of FIG. 3A), the analog switch 10 is connected to the lower end, where the input signal 2 is the next stage buffer 20 Will be printed). When the output voltage is "H", the selection controller 30 turns the signal at the B contact and the C contact (Figs. 3b and 3c) to "H" and the signal at the D point (Fig. 3d) to be "L". Q1 is cut off and transistor Q2 is turned on. Therefore, the input signal 1 applied to the collector terminal of the transistor Q2 is bypassed to the grind through the transistor Q2.

As described above, signals not selected using the two transistors Q1 and Q2 are bypassed to the ground, so that the selected input is not affected by the unselected input and crosstalk does not occur.

The signal in the state in which crosstalk is excluded is output through the buffer 20, which is to prevent the front and rear ends from affecting each other.

As described above, the signal selection circuit according to the present invention selects one of the plurality of input signals according to the voltage output from the selection controller and outputs the next stage, and prevents crosstalk by eliminating the unselected input signals. It can be effective.

Claims (3)

CLAIMS 1. A signal selection arc having switching means for selectively outputting one input signal of a plurality of input signals in accordance with a selection control signal, comprising: a selection control unit for generating the selection control signal to control an operation of the switching means; And a mute circuit for muting input signals applied to input terminals not selected other than the input terminal selected according to the selection control signal. The signal selection arc of claim 1, wherein the mute circuit unit includes a control switch that is turned on or shut down by the selection control signal to mute an input signal or output the signal to the next stage. 2. The signal selection circuit according to claim 1, further comprising an integrating circuit for preventing transient and chattering between said selection control section and said muting circuit section.