KR940001197Y1 - Inverter control circuit of uninterruptible power supply system - Google Patents

Abstract

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Description

Inverter Control Circuit of Uninterruptible Power Supply

1 is a block diagram of a typical uninterruptible power supply.

2 is a circuit diagram of a typical inverter.

3 is a waveform diagram of the main part of the inverter.

4 is a conventional delay circuit diagram used in an inverter.

5 is a waveform diagram of a main part of an inverter using a conventional delay circuit.

6 is an inverter control circuit diagram of an uninterruptible power supply according to the present invention.

7 is a waveform diagram of a main part of an inverter control circuit of an uninterruptible power supply according to the present invention.

* Explanation of symbols for main parts of the drawings

10: rectification and charging unit 20: battery

30 Inverter 100 Sampling Circuit

200: signal transmission circuit 300: first dew control circuit

400: second duty control circuit 110: oscillator

120: first combination unit 130: second combination unit

410: first rectifier 420: second rectifier

T1 to T3: trans NAND to NAND7: NAND gate

The present invention relates to an uninterruptible power supply system (hereinafter referred to as UP S), and more specifically, to the UP S inverter capable of effectively controlling the duty of a pulse (Pulse Wldth Moduilation) pulse applied to the inverter of the UP S. It relates to an inverter control circuit.

UP S can stop or malfunction the equipment due to unexpected power failure such as instantaneous power interruption, instantaneous voltage fluctuation or frequency fluctuation to important facilities such as computer, plant supervisory control device, communication equipment, plant process control device and hospital. AC power supply that supplies high quality power by preventing

General U. P. S is composed of a rectifying and charging section 10, a battery 20 and an inverter 30 as shown in FIG.

The rectifying and charging unit 10 rectifies the AC power while the AC power is being supplied to the battery 30 as a DC power supply, and stops driving when the supply of the AC power is stopped.

When the supply of AC power is stopped as described above, the battery 20 applies the charged power to the inverter 30. The main function of the inverter 30 is to convert the DC power applied from the battery 20 into an AC power and to apply it to a load (not shown).

That is, the inverter is composed of IGBTs (Insulated Gate Bipolar Transistors) (Q1, Q2, Q3, Q4) and a transformer (T1) as shown in FIG. At this time, the pulse P11 of FIG. 3 is applied to the IGBT Q1 and Q4 from a PWM generator (not shown), and the pulse P12 in which the pulse P11 is inverted is applied to the transistors Q2 and Q3. Since it is applied, an alternating current flows through the transformer T1.

However, as described above, the IGBT Q1 is driven back with the IGBT Q2, and when the IGBT Q3 is driven back with the IGBT Q4, the flow of current causes the transformer T1 from the transistor Q1 to flow. Although it must flow through the transistor Q4, as shown in FIG. 3, when the pulses P11 and P12 are inverted correctly, there is a problem that the IGBT is broken due to the delay time.

In the past, a delay circuit as shown in FIG. 4 was used to solve this problem.

That is, the PWM pulse output from the PWM generator is combined with the PWM pulse delayed by the time constant using the time constants of the resistor R1 and the capacitor C1 at the AND gate AND1 to reduce the duty of the PWM pulse. The dead time DT has been formed between the pulses P21 and P22 as shown in FIG. 5 after being reduced and applied to the inverter. However, in the method using a time constant, the dead time is always Since it is not constant, there is a problem that the output voltage of the transformer T1 is still unstable.

In addition, since the power used in the PWM generator is generally in a low voltage state or the power used in the inverter is in a high voltage state, these two circuits cannot be used in common ground.

Therefore, conventionally, a photocoupler using a light emitting diode, a phototransistor, or the like has been used as a method for applying a PWM pulse generated from a PWM generator to the inverter.

However, when the photocoupler is used, the duty of the PWM pulse is not accurately applied to the inverter due to the characteristics of the photocoupler's on and off time, which is another factor causing the output power to become unstable.

The present invention is to solve this problem, the object of the present invention is to provide an inverter control circuit of the U. P. S that can accurately control the dead time of the PWM pulse.

Another object of the present invention is to provide an inverter control circuit of the U. P. S that can accurately apply the PWM pulse generated from the PWM pulse unit to the inverter.

A feature of the present invention for achieving this object is an uninterruptible power supply comprising an inverter for driving according to a PWM pulse of a predetermined frequency to convert an input current voltage into an alternating voltage and outputting the PWM pulse, wherein the PWM pulse is a predetermined frequency A sampling circuit for sampling into a signal, a transformer for applying the PWM pulse to the rear stage, a rectifying section for rectifying the output voltage of the transformer, and a duty control circuit for reducing the output pulse duty ratio of the rectifying section to the inverter, Inverter control circuit of the uninterruptible power supply is configured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is an inverter control circuit diagram of an uninterruptible power supply according to the present invention, and includes a sampling circuit 100, a signal transfer circuit 200, a first duty control circuit 300, and a second duty control circuit 400.

In more detail, the sampling circuit 100 is for sampling the PWM pulse of the PWM pulse unit (not shown) and the inverted PWM pulse in which the PWM pulse is inverted. The oscillator 110, the notifier (not1), and the first , 2 combinations (120, 130).

At this time, the oscillator 110 is composed of a NAND gate (NAND1) having a hysteresis characteristic, and the charge-capacitive capacitor (C2) is configured to oscillate a signal of a predetermined frequency according to the value of the capacitor (C2).

In addition, the output terminal of the notifier (NOT1) is connected to the input terminal of the oscillator 110, the first combination unit 120 combines the PWM pulse of the PWM pulse unit to the output of the oscillator 110 ( NAND2) and the NAND gate NAND3 which combines the PWM pulse of the PWM pulse part with the output of the natator NOT1.

The second combination unit 130 includes a NAND gate NAND4 and an inverted NAND gate NAND5 that combine the PWM pulses with the output of the oscillator 110.

The signal transmission circuit 200 includes a transformer T2 connected to the output terminals of the NAND gates NAND2 and NAND3, and a transformer T3 connected to the output terminals of the NAND gates NAND4 and NAND5. The T2 and T3 are configured to apply the outputs of the first and second combination units 120 and 130 to the first and second duty control circuits 300 and 400.

In addition, the first duty control circuit 300 is for controlling the duty ratio of the output pulse by rectifying the applied voltage of the transformer (T2), to the rectifier 310, the transistor (Q5) and the NAND gate (NAND6). It is composed.

In this case, the rectifier 310 connects the rectifying diodes D1, D2, D3, and D4 to the transformer T2 so that the output of the transformer T2 is rectified and the diode D1. (D2) (D3) (D4) is connected to the switching transistor Q5.

At this time, the transistor Q5 has a predetermined rise time and fall time when driven by its characteristics.

The first duty control circuit 300 is connected to the switch transistor Q5 by connecting a NAND gate NAND6 that operates as a knock gate.

In addition, the second duty control circuit 400 is connected to the transformer T3, and is a rectifier including diodes D5, D6, D7, and D8 in the same manner as the first duty control circuit 300. 410, the switch transistor Q6 and the NAND gate NAND7 are formed in the same manner as the first duty control circuit 300.

Reference numerals R3 and R4 denote bias resistors, and C3 and C4 denote noise canceling capacitors.

In the inverter control circuit of the UPS according to the present invention configured as described above, the oscillation unit 110 of the sampling circuit 100 is applied to the input terminal of the NAND gate NAND1 by the charge / discharge action of the charge / discharge capacitor C2. Since the level of the signal changes, the NAND gate NAND1 outputs a square wave having a predetermined frequency as in the pulse P2 of FIG.

In this case, the PWM generator not shown applies a predetermined square wave to the NAND gate NAND2 like the pulse P1, so that the NAND gate NAND2 outputs the output waveform of the oscillator 110 and the pulse P1. Is combined to output a pulse P3.

In this case, since the output pulse P2 of the oscillator 110 is inverted by the natator NOT1 and applied to the NAND gate NAND3, the NAND gate NAND3 combines the pulse P1 and the inverted signal to generate a pulse (P2). P4) will be output.

Therefore, since a predetermined current path is formed on the primary winding side by the NAND gates NAND2 and NAND3 in the transformer T2, a predetermined voltage due to the turns ratio is induced in the secondary winding. That is, the reason for using the transformer (T2) is as described above in the prior art, the PWM generator and the inverter is insulated from each other, the PWM pulse is applied to the inverter from the PWM generator from the PWM transfer in the present application. The transformer is used as a means of doing so.

The reason why the PWM pulses are sampled as a predetermined frequency is to facilitate the transfer of the PWM pulses because the transmission characteristics of the transformer are increased as the high frequency component is increased.

In this case, as the pulses induced in the secondary winding of the transformer T2 are the pulses sampled by the PWM pulse P1 by the pulse P1 as described above, the IGBT (Q1) (Q2) of the inverter. It cannot be applied as it is to (Q3) (Q4). The present application was to rectify the sampled pulses that are induced in the transformer (T2). Therefore, the waveform output from the diodes D1, D2, D3, and D4 of the rectifier 310 may have the same shape as the original PWM pulse P1 like the pulse P5.

However, when the transistor Q5 is driven by the pulse P5, the collector side of the transistor Q5 inverts the pulse P5 to output the pulse P6, and the NAND gate NAND6 outputs the pulse (P5). P6) is inverted again and output as a pulse P7.

At this time, the duty width of the pulses P5 and P7 is different because the delay time due to the rise time and the fall time generated when the transistor Q5 is driven by the pulse P5. This is because the duty width is reduced.

In addition, the duty width of the pulse P5 is reduced than the duty width of the pulse P1 because the power loss due to the characteristics of the transformer occurs when the pulses P3 and P4 are transmitted by the transformer T2. This is because a slight reduction in the duty width occurs.

The PWM pulse inverted PWM pulse P8 is processed in the same way as the PWM pulse of the PWM generator is processed in the first combination unit 120, the transformer (T2) and the first duty width control circuit 300. When the second combination unit 130, the transformer T3, and the second dury width control circuit 400 process the same, the pulse width P9 of which the dury width is reduced is output like the pulse P7.

Comparing the pulses P7 and P9, it can be seen that a predetermined dead time DT occurs.

Therefore, when the pulses P7 and P9 are applied to the IGBTs Q1 and Q4 of the Dean butter, the IGBTs Q1 and Q4 are not simultaneously turned on.

As described above, when the AC direct current voltage of the inverter is stabilized by insulating the PWM pulse from the inverter by using a transformer, the output voltage is further stabilized by generating a dead time using a delay time due to the characteristics of the transistor.

Claims (4)

An uninterruptible power supply comprising an inverter which drives according to a PWM pulse of a predetermined frequency and converts an input DC voltage into an AC voltage and outputs the same, wherein the PWM pulse and the inverted PWM pulse in which the PWM pulse is inverted are converted into a signal of a predetermined frequency. A sampling circuit for sampling, a first and second transformers, a signal transfer circuit for applying the PWM pulses and the inverted PWM pulses to the rear stage, rectifying the output voltage of the first transformer, and controlling the duty ratio of the output pulses. The first duty control circuit applied to the inverter and the second duty control circuit rectifying the output voltage of the second transformer and controlling the duty ratio of the output pulse to the inverter. Control circuit. The oscillator of claim 1, wherein the sampling circuit comprises: an oscillator for oscillating a signal of a predetermined frequency, a first gate for inverting the output of the oscillator, a first combination unit for combining the output of the first gate with the PWM pulse; And a second combining unit for combining the output of the first gate to the inverting PWM pulses. The output circuit of claim 1, wherein the first duty control circuit comprises: a first rectifying unit rectifying the output of the first transformer, a switching transistor switched according to the output of the first rectifying unit, and an output of the first switching transistor. Inverter control circuit of the uninterruptible power supply comprising a second gate for inverting. The switching circuit of claim 1, wherein the second duty control circuit comprises: a second rectifying unit rectifying the output of the second transformer, a second switching transistor switched according to the output of the second rectifying unit, and the second switching transistor. Inverter control circuit of the uninterruptible power supply comprising a third gate to invert the output of the.