KR930024288A - Clock Duty Detection and Adjustment Circuit - Google Patents

Clock Duty Detection and Adjustment Circuit Download PDF

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Publication number
KR930024288A
KR930024288A KR1019920008316A KR920008316A KR930024288A KR 930024288 A KR930024288 A KR 930024288A KR 1019920008316 A KR1019920008316 A KR 1019920008316A KR 920008316 A KR920008316 A KR 920008316A KR 930024288 A KR930024288 A KR 930024288A
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KR
South Korea
Prior art keywords
clock
duty
duty ratio
output
inverted
Prior art date
Application number
KR1019920008316A
Other languages
Korean (ko)
Other versions
KR940007297B1 (en
Inventor
김학근
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019920008316A priority Critical patent/KR940007297B1/en
Publication of KR930024288A publication Critical patent/KR930024288A/en
Application granted granted Critical
Publication of KR940007297B1 publication Critical patent/KR940007297B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 클럭 듀티(Clock Duty)검출 및 조정회로에 관한 것으로, 종래에는 정상적인 듀티를 갖는 신호가 입력되더라도 내부의 버퍼 사이즈에 의하여 듀티가 어긋날 수도 있고, 또 외부에서 입력되는 듀티비가 어긋나서 입력되어지기도 하는데 이때 어긋난 듀티비에 의하여 내부동작이 영향을 받아 오동작할 수 있는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duty detection and adjustment circuit. In the related art, even when a signal having a normal duty is input, the duty may be shifted depending on the internal buffer size, and the duty ratio input from the outside is shifted. At this time, the internal operation is affected by the shifted duty ratio, which may cause a malfunction.

이와같은 종래의 결함을 감안하여 본 발명은 클럭 듀티가 어긋날 경우 그것을 검출하여 출력하면 그 출력을 디코딩한 뒤 듀티비를 정상적으로 조정하여 내부클럭으로서 사용함으로써 오동작을 방지하도록 한 효과가 있다.In view of such a conventional defect, the present invention has the effect of preventing malfunction by detecting and outputting the clock duty when it is out of order, by decoding the output and adjusting the duty ratio normally to use it as an internal clock.

Description

클럭 듀티 검출 및 조정회로Clock Duty Detection and Adjustment Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 클럭 듀티 검출 및 조정회로 블럭도, 제3도는 제2도에 의한 상세회로도, 제4도는 본 발명에 의한 듀티비검출부의 각부 파형도.2 is a block diagram of the clock duty detection and adjustment circuit of the present invention, FIG. 3 is a detailed circuit diagram according to FIG. 2, and FIG. 4 is a waveform diagram of each part of the duty ratio detection unit according to the present invention.

Claims (3)

입력되는 외부클럭의 포지티브 대 네가티브의 클럭듀티비를 검출하는 듀티비검출부(100)와, 이 듀티비검출부(100)의 검출상태를 종류별로 디코딩하는 디코딩부(200)와, 디코딩부(200)의 출력 및 외부클럭에 따라 비정상 상태의 듀티비를 정상상태의 듀티비로 조정하여 출력하는 듀티조정부(300)와, 이 듀티조정부(300)을 통해 조정된 클럭과 원클럭을 조건에 따라 선택하여 내부클럭으로서 클럭버퍼로 출력하는 멀티플랙서(400)로 구성됨을 특징으로 하는 클럭 듀티 검출 및 조정회로.A duty ratio detector 100 for detecting a positive to negative clock duty ratio of an external clock to be input, a decoder 200 for decoding the detection state of the duty ratio detector 100 by type, and a decoder 200 In accordance with the output and the external clock of the duty ratio of the abnormal state to adjust the duty ratio of the normal state to output the duty adjustment unit 300, and the clock and one clock adjusted through the duty adjustment unit 300 according to the condition to select And a multiplexer (400) for outputting the clock buffer as a clock. 제1항에 있어서, 상기 듀티조정부(300)는 반전 및 비반전시키는 인버터(I1), (I2)의 출력을 온,오프동작에 따라 통과시키는 엔모스트랜지스터(MN1)(MN2)와, 상기 엔모트랜지스터(MN1)(MN2)를 통해 입력된 외부 클럭에 대해 일정시간 지연하는 제3지연부(501)와, 이 제3지연부(501)의 지연출력을 반전하는 인버터(I3)와, 이 인버터(I3)의 반전출력과 반전 또는 비반전된 외부클럭을 오아링하는 오아게이트(OR2)로 구성됨을 특징으로 하는 클럭 듀티 검출 및 조정회로.The method of claim 1, wherein the duty adjusting unit 300 includes a NMOS transistor (MN 1) to pass according to the inverted and non-inverted for turning on and off operation of the output of the inverter (I 1), (I 2) (MN 2) And a third delay unit 501 for delaying a predetermined time with respect to an external clock input through the NMO transistor MN 1 and MN 2 , and an inverter for inverting the delay output of the third delay unit 501. I 3) and the inverter (I 3) and the inverted output inverted or non-inverted external clock Iowa Iowa ring gate (oR 2) clock duty detection and adjustment circuit, characterized by consisting of a that of. 제2항에 있어서, 상기 제3지연부(501)는 입력되는 신호가 로우에서 하이로의 전송시엔 지연없이 전달하고 하이에서 로우로의 전송시엔 0.2f만큼 지연시켜 전달하도록 함을 특징으로 하는 클럭 듀티 검출 및 조정회로.3. The clock duty of claim 2, wherein the third delay unit 501 transmits the input signal without delay when transmitting from low to high and delays 0.2f when transferring from high to low. Detection and adjustment circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920008316A 1992-05-16 1992-05-16 Clock duty detecting and controlling circuit KR940007297B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920008316A KR940007297B1 (en) 1992-05-16 1992-05-16 Clock duty detecting and controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920008316A KR940007297B1 (en) 1992-05-16 1992-05-16 Clock duty detecting and controlling circuit

Publications (2)

Publication Number Publication Date
KR930024288A true KR930024288A (en) 1993-12-22
KR940007297B1 KR940007297B1 (en) 1994-08-12

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Application Number Title Priority Date Filing Date
KR1019920008316A KR940007297B1 (en) 1992-05-16 1992-05-16 Clock duty detecting and controlling circuit

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KR (1) KR940007297B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329637B1 (en) * 1997-04-16 2002-08-21 주식회사 하이닉스반도체 Channel card for base station in mobile communication system capable of compensating duty ratio of system clock

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329637B1 (en) * 1997-04-16 2002-08-21 주식회사 하이닉스반도체 Channel card for base station in mobile communication system capable of compensating duty ratio of system clock

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Publication number Publication date
KR940007297B1 (en) 1994-08-12

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