KR930022878A

KR930022878A - Display

Info

Publication number: KR930022878A
Application number: KR1019920006849A
Authority: KR
Inventors: 김정훈
Original assignee: 이헌조; 주식회사 금성사
Filing date: 1992-04-23
Publication date: 1993-11-24

Abstract

본 발명은 화면표시장치에 관한 것으로, 종래에서는 와이드(16:9)티브이에서 기존화면(4:3)시청시 수평을 축소보상하도록 리모콘 버턴을 눌러야 하는 불편함이 있었다.The present invention relates to a screen display device, and in the related art, it is inconvenient to press a remote control button to reduce the horizontal compensation when viewing an existing screen (4: 3) from a wide (16: 9) TV.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 와이드화면과 기존화면을 수신신호의 상태에 따라서 자동으로 화면을 보상하여 디스플레이한 것이다.The present invention is to compensate for the display of the wide screen and the existing screen automatically in accordance with the state of the received signal in order to solve the conventional problems as described above.

즉, 방송국에서 수직귀선기간에 전송해주는 디지탈신호를 검출하여 만약 기준화면비이면 마이콤에 인식한후 제어하여 메모리를 사용한 압축방법과 수평편향사이즈 축소등의 2가지 방법을 통해 사이즈 보상을 행함으로써, 와이드 텔레비젼 시스템에 적용되게 한다.That is, the broadcasting station detects the digital signal transmitted during the vertical retrace period, and if it is the reference aspect ratio, recognizes it by the microcomputer and controls it to perform size compensation through two methods, a compression method using a memory and a horizontal deflection size reduction. To be applied to television systems.

Description

Display

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 와이드화면과 기존화면의 비교도, 제3도는 본 발명 화면표시장치 구성도, 제4도는 제3도의 일실시도, 제5도는 제4도의 일실시도, 제5도는 제4도의 편향부 상세도, 제6도는 제3도 및 제4도의 화면비데이타검출부의 상세도, 제7도의 (가) 내지(다)는 제5도의 각부 동작 파형도, 제8도의 (가) 내지 (다)는 제6도의 각부 동작 파형도.2 is a diagram illustrating a comparison between a wide screen and an existing screen, and FIG. 3 is a block diagram of the present invention. FIG. 4 is an embodiment of FIG. 3, FIG. 5 is an embodiment of FIG. 4, and FIG. Fig. 6 is a detailed view of the screen data detection unit of Figs. 3 and 4, Fig. 7A through Fig. 7A and Fig. 5A and 5B show the operation waveforms of each part of Fig. 8, Fig. 8A through C. Figs. Fig. 6 is an operation waveform diagram of each part.

Claims

An analog / digital converter 10 for converting an analog signal of an input video signal into a digital signal according to the light frequency oscillator 50, and a memory unit for storing the output signal of the analog / digital converter 10 according to the light frequency. (20) and a selector switch unit (80) for selecting the signals of the first second lead frequency oscillator (60) and (70) according to the control voltage of the microcomputer (90) and outputting them to the memory unit (20); The output signal of the digital / analog converter 30 and the digital / analog converter 30 for converting the stored signal of the memory unit 20 into an analog signal according to the read frequency selected by the selection switch unit 80 are signaled. The video signal processor 40 outputs the R, G, and B color signals, and detects the non-discrimination digital data carried in the vertical retrace period of the video signal to the integrated-adjustment control (I ² C) bus. Aspect ratio to be output to the microcomputer 90 And a deflection unit 10 for adjusting the data of the screen detection unit 100 to horizontal size deflection data and outputting the data to the memory unit 20 and the image signal processing unit 40. Display device.

A deflection unit that reads the screen ratio data detected by the screen ratio data detection unit 100 from the microcomputer 90 using an I ² C bus, and then controls the horizontal size data to set the horizontal size of the image signal processor 40 according to the received aspect ratio signal. A display device, characterized in that consisting of (110).

The apparatus of claim 1 or 2, wherein the screen ratio data detecting unit (100) comprises a data extracting unit (101) and a data processing unit (102). The data extracting unit (101) extracts a synchronizing portion of an image signal and synchronizes the buffer. The data portion is output from the synchronous slice section 101A output through the section 101B, the high pass compensation section 101C for compensating the digital signal edge portion of the synchronous slice section 101A, and the high pass compensation section 101C. And a data slice unit 101D for extracting and outputting the data through the data buffer unit 101E, and an oscillation unit 101F for generating a clock. The data processing unit 102 includes a data buffer according to the clock of the oscillation unit 101F. data detector (102A) and, I ² I ² C bus interfaces that format the data from the C bus for storing a part (101E), a memory unit 103 and then retains the output data through a memory interface section (102B) of Section 102D and I ² C bus control after the data is recognized. And a character generator 102D for generating character information.

※ Note: The disclosure is based on the initial application.