KR930020428A - V D Phi's Power Saving Method - Google Patents

V D Phi's Power Saving Method Download PDF

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Publication number
KR930020428A
KR930020428A KR1019920004211A KR920004211A KR930020428A KR 930020428 A KR930020428 A KR 930020428A KR 1019920004211 A KR1019920004211 A KR 1019920004211A KR 920004211 A KR920004211 A KR 920004211A KR 930020428 A KR930020428 A KR 930020428A
Authority
KR
South Korea
Prior art keywords
power
power supply
supply unit
signal
power saving
Prior art date
Application number
KR1019920004211A
Other languages
Korean (ko)
Inventor
박동성
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920004211A priority Critical patent/KR930020428A/en
Publication of KR930020428A publication Critical patent/KR930020428A/en

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Abstract

본 발명은 VDP의 전원 제어 기술에 관한 것으로, 사용자의 부주위에 의해 불필요하게 시스템에 전원이 공급되어 기기의 수명이 단축되고, 전력이 낭비되는 것을 방지하기 위한 수단으로써 소정시간내에 수직동기신호가 입력되지 않으면 전원 공급부(5)로 부터 전원 구동부(7)에 공급되는 전원을 차단하고, 소정치를 상회하기 이전에 수직동기신호(Vsyn)가 입력되면 현재까지 카운트된 값을 리세트시켜 계속해서 정상적인 플레이가 이루어지게 하였다.The present invention relates to a power control technology of the VDP, and the vertical synchronous signal is input within a predetermined time as a means for preventing the unnecessary life of the device and the waste of power by supplying power to the system unnecessarily around the user. If not, turn off the power supplied from the power supply unit 5 to the power supply unit 7, and if the vertical synchronizing signal Vsyn is input before exceeding the predetermined value, reset the value counted so far to continue normal operation. Play was done.

Description

브이 디 피의 절전 방법V D Phi's Power Saving Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 절전 방법이 적용되는 브이 디 피의 블록도.1 is a block diagram of a VD to which the power saving method of the present invention is applied.

제2도는 본 발명의 신호 흐름도.2 is a signal flow diagram of the present invention.

Claims (2)

파워가 온되는 시점에서 카운트 동작을 시작함과 아울러, 재생신호를 스캔하여 그 카운트 값이 소정치를 상회할때까지 재생신호가 입력되지 않으면 전원 공급부(5)로 부터 전원 고동부(7)에 공급되는 전원을 차단하고, 그 카운트 값이 소정치를 상회하기 이전에 재생신호가 입력되면 현재까지 카운트 된 값을 리세트시키는 것을 특징으로 하는 브이 디 피의 절전 방법.When the power is turned on, the count operation starts and the playback signal is scanned. If the playback signal is not input until the count value exceeds a predetermined value, the power supply unit 5 supplies the power supply unit 7 with the count signal. A power saving method of a VDP, characterized in that the power supply to be supplied is cut off, and if a reproduction signal is input before the count value exceeds a predetermined value, the count value so far is reset. 제1항에 있어서, 재생신호를 수직동기신호로 하는 것을 특징으로 하는 브이 디 피의 절전 방법.The method of claim 1, wherein the reproduction signal is a vertical synchronization signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920004211A 1992-03-14 1992-03-14 V D Phi's Power Saving Method KR930020428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920004211A KR930020428A (en) 1992-03-14 1992-03-14 V D Phi's Power Saving Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920004211A KR930020428A (en) 1992-03-14 1992-03-14 V D Phi's Power Saving Method

Publications (1)

Publication Number Publication Date
KR930020428A true KR930020428A (en) 1993-10-19

Family

ID=67257026

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920004211A KR930020428A (en) 1992-03-14 1992-03-14 V D Phi's Power Saving Method

Country Status (1)

Country Link
KR (1) KR930020428A (en)

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