KR930018946U - Dual monitor image stabilization circuit - Google Patents

Dual monitor image stabilization circuit

Info

Publication number
KR930018946U
KR930018946U KR2019920000631U KR920000631U KR930018946U KR 930018946 U KR930018946 U KR 930018946U KR 2019920000631 U KR2019920000631 U KR 2019920000631U KR 920000631 U KR920000631 U KR 920000631U KR 930018946 U KR930018946 U KR 930018946U
Authority
KR
South Korea
Prior art keywords
image stabilization
stabilization circuit
monitor image
dual monitor
dual
Prior art date
Application number
KR2019920000631U
Other languages
Korean (ko)
Other versions
KR940007704Y1 (en
Inventor
서정석
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR92000631U priority Critical patent/KR940007704Y1/en
Publication of KR930018946U publication Critical patent/KR930018946U/en
Application granted granted Critical
Publication of KR940007704Y1 publication Critical patent/KR940007704Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/63—Generation or supply of power specially adapted for television receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/234—Indexing scheme relating to amplifiers the input amplifying stage being one or more operational amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
KR92000631U 1992-01-17 1992-01-17 Picture stabilization circuit of dual monitor KR940007704Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92000631U KR940007704Y1 (en) 1992-01-17 1992-01-17 Picture stabilization circuit of dual monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92000631U KR940007704Y1 (en) 1992-01-17 1992-01-17 Picture stabilization circuit of dual monitor

Publications (2)

Publication Number Publication Date
KR930018946U true KR930018946U (en) 1993-08-21
KR940007704Y1 KR940007704Y1 (en) 1994-10-22

Family

ID=19328018

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92000631U KR940007704Y1 (en) 1992-01-17 1992-01-17 Picture stabilization circuit of dual monitor

Country Status (1)

Country Link
KR (1) KR940007704Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010057334A (en) * 1999-12-22 2001-07-04 이형도 Graphic adaptor including double output ports

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010057334A (en) * 1999-12-22 2001-07-04 이형도 Graphic adaptor including double output ports

Also Published As

Publication number Publication date
KR940007704Y1 (en) 1994-10-22

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19980925

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee