KR930013993A - Memory board with error correction - Google Patents
Memory board with error correction Download PDFInfo
- Publication number
- KR930013993A KR930013993A KR1019910024250A KR910024250A KR930013993A KR 930013993 A KR930013993 A KR 930013993A KR 1019910024250 A KR1019910024250 A KR 1019910024250A KR 910024250 A KR910024250 A KR 910024250A KR 930013993 A KR930013993 A KR 930013993A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- memory
- address
- data
- count
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
Abstract
본 발명은 에러정정 기능을 갖는 메모리 보드에 관한 것으로서, 특히 전원공급(power on)이 이루어진 다음 메모리에 저장된 데이타를 독출할때 임의의 체크비트(chech bits)로 인한 에러 발생을 방지하기 위하여 메모리의 데이타 저장영역과 정정 코드 영역을 특정한 값으로 초기화 시키는 메모리 보드에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory board having an error correction function. In particular, the present invention relates to a memory board in order to prevent an error caused by random check bits when reading data stored in the memory after power on. A memory board initializes data storage area and correction code area to specific values.
메인 시스템의 데이타를 저장 및 독출하는 데이타 저장 영역과 이 데이타와 연계된 체크비트를 저장하는 정정코드 영역을 갖는 메모리(10)와, 데이타의 독출 및 기입시 상기 체크 비트를 검색하여 에러여부를 검출하고 또한 에러 정정 및 검출기(20)를 구비한 메모리 보드에 있어서, 전원의 초기 공급 신호를 받아서 다음의 스텝을 수행하는 제어부(30)와, (a)상기 초기공급 신호에 응답하여 레지스터 클리어 신호를 발생하는 스텝과, (b)이어 상기 에러정정 및 검출기(20)에서 상기 체크비트를 출력하는 체크비트 생성신호를 상기 검출기(20)로 제공하는 스텝과, (c) 이어 RAS(row address strobe)활성신호와, 데이타 기입 제어신호를 생성하여 상기 메모리(10)로 제공하는 스텝과, (d)이어 선택신호를 발생한 다음 CAS(column address strobe)활성신호를 상기 메모리(10)로 제공하는 스텝 및, (e)카운트 아웃(count-out)신호 여부를 검출하여 이 신호가 존재할 경우 초기화 과정을 종료하고, 반대로 상기 신호가 존재하지 않을 경우 1 카운트 업(1 count up)동기용 신호를 출력하는 스텝.A memory 10 having a data storage area for storing and reading data of the main system and a correction code area for storing check bits associated with the data, and searching for and checking the check bits when reading and writing data; A memory board having a detection and error correction and detector (20), comprising: a control unit (30) for receiving an initial supply signal of power and performing a next step; and (a) a register clear signal in response to the initial supply signal. (B) providing the check bit generation signal for outputting the check bit from the error correction and detector 20 to the detector 20, and (c) row address strobe Generating an activation signal, a data write control signal to the memory 10, and (d) generating a selection signal and then providing a CAS (column address strobe) activation signal to the memory 10. Step (e) Detect whether or not the count-out signal is detected, and if the signal exists, the initialization process is terminated; otherwise, if the signal does not exist, one count up synchronization signal is output. Step to do.
상기 초기공급신호에 의해 클리어 되고 상기 1카운트 업 신호에 의해 동기되면서 소정 비트의 어드레스 신호를 1그룹으로 하여 2그룹의 어드레스 신호를 출력하는 어드레스 발생수단과, 상기 선택신호에 의해 제어되어서 두 그룹의 어드레스 신호중 1그룹을 출력하는 어드레스 선택수단 및, 상기 레지스터 클리어 신호에 의해 상기 메모리(10)의 데이타 저장영역에 "0"의 값을 제공하게 하는 레지스터(60)를 구비한 것을 특징으로 한다.Address generating means for outputting two groups of address signals by setting the address signal of a predetermined bit into one group while being cleared by the initial supply signal and synchronized by the one count-up signal, and controlled by the selection signal, Address selection means for outputting one group of address signals, and a register 60 for providing a value of " 0 " to the data storage area of the memory 10 by the register clear signal.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명에 의한 메모리 보드의 회로도.1 is a circuit diagram of a memory board according to the present invention.
제2도는 제1도의 주요부분에서 입출력되는 신호의 타이밍도,2 is a timing diagram of signals inputted and outputted from the main part of FIG.
제3도는 제1도의 제어부에서 수행되는 기능제어 프로그램의 순서도.3 is a flowchart of a function control program executed by the controller of FIG.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024250A KR940009755B1 (en) | 1991-12-24 | 1991-12-24 | Memory board having error correction function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024250A KR940009755B1 (en) | 1991-12-24 | 1991-12-24 | Memory board having error correction function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930013993A true KR930013993A (en) | 1993-07-22 |
| KR940009755B1 KR940009755B1 (en) | 1994-10-17 |
Family
ID=19325908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910024250A KR940009755B1 (en) | 1991-12-24 | 1991-12-24 | Memory board having error correction function |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940009755B1 (en) |
-
1991
- 1991-12-24 KR KR1019910024250A patent/KR940009755B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940009755B1 (en) | 1994-10-17 |
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Payment date: 19980929 Year of fee payment: 5 |
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