KR930009259A

KR930009259A - Linear interpolation circuit

Info

Publication number: KR930009259A
Application number: KR1019910017887A
Authority: KR
Inventors: 김동호
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1991-10-11
Filing date: 1991-10-11
Publication date: 1993-05-22

Abstract

본 발명은 D/A변환된 아날로그 신호에 불연속성을 줄여 이에 따른 잡음을 감소시키는 리니어 보간 회로로써, 구성은 디지털 신호를 제1클럭에 의해 동작하는 지연기(U₁,U₅)와, 지연기(U₅)의 출력을 제1클럭에 의해 동작하는 지연기(U₆)와, 상기 디지털신호와 지연기(U₁)의 출력을 입력으로 하는 가산기와, 가산기의 출력을 와이어 쉬프트(+2)하고 제1클럭과 제2클럭에 의해 동작하는 지연기(U₄)와, 상기 지연기(U₆)의 출력과 지연기 (U₄)의 출력을 제2클럭에 의해 동작하는 D/A변환기로 이루어진다.The present invention is a linear interpolation circuit that reduces discontinuities in a D / A-converted analog signal, thereby reducing noise. The configuration includes delayers U ₁ and U _{5 for} operating a digital signal by a first clock, ₍₅ U) and the retarder ₍₆ U) operated by the output of the first clock, the wire adder and an output of the adder to an output of the digital signal and the delay unit (U ₁₎ to the shift input (+2 D / A which operates the delay unit U ₄ operated by the first clock and the second clock, and the output of the delay unit U ₆ and the output of the delay unit U ₄ by the second clock. Made of a transducer.

Description

Linear interpolation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 종래의 D/A변환된 아날로그 신호 설명도,2 is a schematic diagram of a conventional D / A converted analog signal,

제3도는 본 발명의 D/A변환 블럭도,3 is a block diagram of a D / A conversion of the present invention;

제4도는 본 발명에 따른 클럭 타이밍도.4 is a clock timing diagram in accordance with the present invention.

Claims

The output of the A / D converter, and a retarder retarder (U ₅₎ by the (U _1, U _5), and a first clock for delaying the A / D converter output by the first clock, which operates by the first clock A delay unit (U ₆ ) for delaying the signal, an adder for inputting the output of the digital signal and the delay unit (U ₁ ), a wire shift (+2) of the output of the adder, and the first and second clocks. A delay unit (U ₄ ) sent to the D / A converter and a D / A converter converting the output of the delay unit and the output of the delay unit (U ₄ ) to an analog signal by a second clock as an input. Linear interpolation circuit.

The linear interpolation circuit according to claim 1, wherein the second clock has a clock frequency increased by attaching a multiplier to the first clock.

※ Note: The disclosure is based on the initial application.