KR930008906B1 - Isolation method of semiconductor device - Google Patents
Isolation method of semiconductor device Download PDFInfo
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- KR930008906B1 KR930008906B1 KR1019900016256A KR900016256A KR930008906B1 KR 930008906 B1 KR930008906 B1 KR 930008906B1 KR 1019900016256 A KR1019900016256 A KR 1019900016256A KR 900016256 A KR900016256 A KR 900016256A KR 930008906 B1 KR930008906 B1 KR 930008906B1
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- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
Description
제 1a - 1d 도는 종래의 아이솔레이션 공정순서도.1a-1d is a conventional isolation process flow chart.
제 2 도는 본 발명에 따른 아이솔레이션 공정을 설명하기 위한 평면도.2 is a plan view for explaining an isolation process according to the present invention.
제 3a - 3e 도는 본 발명에 따른 아이솔레이션 공정순서도.3a-3e or a flow chart of the isolation process according to the invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : P형 실리콘기판 11 : 게이트10: P-type silicon substrate 11: gate
12 : LTO 13 : 소오스/드레인12: LTO 13: Source / Drain
14 : 배리어 산화막 15 : SOG14 barrier oxide film 15 SOG
16 : 절연체 17 : 트렌치 아이솔레이션 영역16: insulator 17: trench isolation region
18 : 게이트 커팅층18: gate cutting layer
본 발명은 반도체 제조에 관한 것으로 특히 서브미크론(Submicron) CMOS 집적소자에 적당하도록 한 반도체 소자의 아이솔레이션(Isolation) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to semiconductor manufacturing, and in particular, to a method of isolating semiconductor devices adapted to be suitable for submicron CMOS integrated devices.
종래의 소자 격리기술 즉 아이솔레이션 기술은 여러가지가 있으나 그중 대표적인 LOCOS(Local Oxidation on Silicon : 국부산화)에 관해 기술하면 다음과 같다.Conventional device isolation techniques, i.e., isolation techniques, are available, but a typical LOCOS (Local Oxidation on Silicon: localization) is described as follows.
먼저 제 1a 도에서와 같이 실리콘기판(1)위에 패드 산화막(Pad Oxide)(2)을 성장시킨 후 Si3N4(3)를 LPCVD 방법으로 증착한다.First, as shown in FIG. 1A, a pad oxide film 2 is grown on the silicon substrate 1, and then Si 3 N 4 (3) is deposited by the LPCVD method.
그 다음 제 1b 도에서와 같이 액티브(소자가 형성될 영역)마스크 작업으로 소자가 형성될 영역을 정의하고 Si3N4(3)를 식각한다.Then, as shown in FIG. 1B, an active (region where the device is to be formed) mask operation is used to define a region where the device is to be formed and to etch Si 3 N 4 (3).
그다음 포토레지스터(4)를 제거하고 O2혹은 H2O 등을 이용하여 산화를 시키는데 Si3N4(3)는 산화가 잘 되지 않는 반면 실리콘기판(1)은 산화막 성장이 용이하므로 제 1c 도에서와 같이 Si3N4가 없는 영역에서만 국부적으로 두꺼운 산화막(5)이 성장하게 된다.Then, the photoresist 4 is removed and oxidized using O 2 or H 2 O. Si 3 N 4 (3) is not easily oxidized, whereas the silicon substrate 1 is easy to grow an oxide film. As in the above, the locally thick oxide film 5 grows only in the region without Si 3 N 4 .
그 다음 핫(Hot) H3PO4(약 155℃)로 Si3N4를 제거하고 패드산화막을 차례로 제거하면 제 1d 도에서와 같이 국부산화막이 형성되어 소자간 격리가 이루어지게 된다.Then, when Si 3 N 4 is removed by hot H 3 PO 4 (about 155 ° C.) and the pad oxide film is sequentially removed, a local oxide film is formed as shown in FIG.
단 주의해야할 것은 종래는 소자격리를 먼저 수행한 후 게이트, 소오스-드레인을 차례로 형성해가는 것이다.It should be noted, however, that device isolation is performed first, and then gates and source-drains are sequentially formed.
그런데 아이솔레이션 방법중 상기와 같은 LOCOS의 경우는 서브미크론에는 부적절하므로(버즈빅(Bird's beak)등에 의해) SWAMI(Side Wall Masked Isolation), STLO, POX(Polysilicon Oxidation), BOX(Buried Oxide) 아이솔레이션, 트렌치등 여러가지 방법이 동원되고 있으나 공정이 복잡하여 여러가지 문제점이 많이 내포되어 있는 단점이 있다.However, LOCOS as described above is not suitable for submicron (by Bird's beak), so it is SWAMI (Side Wall Masked Isolation), STLO, POOX (Polysilicon Oxidation), BOX (Buried Oxide) isolation, trench Various methods have been mobilized, but there are disadvantages in that the process is complicated and there are many problems.
본 발명은 이러한 단점을 해결하기 위해 아이솔레이션 즉 소자간의 격리를 종래와 다르게 게이트, 소오스-드레인 형성후에 SOG(Spin-On-Glass)를 배리어(Barrier)로 사용하여 쉘로우 트렌치 에치(shallow trench etch)/리필(refill)을 수행하도록 한 셀프 얼라인 서브미크론 소자 아이솔레이션 방법으로써 이하 첨부도면을 참조하여 상세히 설명하면 다음과 같다.In order to solve this drawback, the present invention uses a shallow trench etch (Isolation) between isolation and device isolation using a spin-on glass (SOG) as a barrier after gate and source-drain formation. A self-aligned submicron device isolation method for refilling is described in detail with reference to the accompanying drawings as follows.
제 2 도의 평면도 및 제 2 도의 A-A'선에 따른 단면도인 제 3 도를 참고하여 본 발명의 아이솔레이션 방법을 공정순서별로 차례로 설명하면(여기서는 NMOS FET에 관해서만 설명하기로 함), 일반적인 공정기술에 따라 제 2a 도의 게이트패턴을 이용하여 P형 실리콘기판(10)위에 게이트절연막과 게이트라인(11) 및 캡산화막(12)까지 형성한 후, 제 3a 도에서와 같이 n+소오스-드레인 이온주입을 행하여 n+소오스-드레인영역(13)을 형성한다.Referring to FIG. 3, which is a plan view of FIG. 2 and a cross-sectional view taken along the line A-A 'of FIG. 2, the isolation method of the present invention is described in order of process order (here, only the NMOS FET will be described). According to the technique, a gate insulating film, a gate line 11, and a cap oxide film 12 are formed on the P-type silicon substrate 10 using the gate pattern of FIG. 2a, and then n + source-drain ions as shown in FIG. 3a. Implantation is performed to form n + source-drain regions 13.
그리고 제 3b 도에서와 같이 결과물상에 포토레지스트를 도포하고 제 2b 도와 같은 게이트 컷팅 마스크(Gate Cutting Mask)를 적용한 사진식각공정에 의해 게이트라인의 소정부위를 식각하여 부분적으로 게이트를 남기고 이어서 상기 포토레지스트패턴이 남아 있는 상태에서 게이트영역끼리의 격리를 위한 보론등의 이온주입을 수행하여 소자격리용 이온주입영역(제 2c 도 참조부호 21)을 형성한 후, 포토레지스트패턴을 제거하고 이온주입에 따른 활성화를 위한 소오스-드레인 어닐링을 행한다.Then, as shown in FIG. 3b, a photoresist is applied on the resultant, and a predetermined portion of the gate line is etched by a photolithography process using a gate cutting mask as shown in FIG. In the state where the resist pattern remains, ion implantation such as boron for isolation of the gate regions is performed to form an ion isolation region for isolation (see FIG. 2C), and then the photoresist pattern is removed and ion implanted. Source-drain annealing is performed for subsequent activation.
이어서 후속공정에서 형성될 SOG의 배리어(Barrier) 역할을 하도록 하기 위해 상기 결과물 전면에 산화막(14)을 형성한 다음, SOG막(15)을 도포(Coat)하고 베이크(Bake)한다.Subsequently, an oxide film 14 is formed on the entire surface of the product to serve as a barrier of the SOG to be formed in a subsequent process, and then the SOG film 15 is coated and baked.
그 다음 제 3c 도에서와 같이 SOG막(15)을 에치백(Etchback)하여 아이솔레이션 영역을 정의하는데 이때 상기 SOG를 에치백하게 되면 다른 영역보다 SOG막이 얇게 형성된 곳인 게이트와 게이트 사이의 기판이 먼저 노출되게 되고 이에 따라 아이솔레이션영역은 셀프 얼라인 즉 자기정열되어 형성되게 된다.Next, as shown in FIG. 3C, the SOG film 15 is etched back to define an isolation region. When the SOG is etched back, the substrate between the gate and the gate, which is the place where the SOG film is thinner than other regions, is exposed first. Accordingly, the isolation region is formed by self-alignment, that is, self-alignment.
그 다음 제 3d 도에서와 같이 상기 자기정렬된 아이솔레이션영역의 기판을 식각하여 쉘로우(shallow)트렌치를 형성하고(제 2c 도 참조부호 22참조), 소자간 완전격리를 위한 채널스탑 이온주입을 상기 트렌치 하부에 행하고 그다음 제 3e 도에서와 같이 트렌치를 절연막으로 리필(refill)시키고 결과물 전면에 절연층(LTO/BPSG)(16)을 증착하고 플로우잉(Flowing)공정을 수행한다.Then, as shown in FIG. 3d, the substrate of the self-aligned isolation region is etched to form a shallow trench (see reference numeral 22 of FIG. 2c), and channel stop ion implantation for complete isolation between devices is performed. In the lower part, the trench is then refilled with an insulating film as shown in FIG. 3E, an insulating layer (LTO / BPSG) 16 is deposited on the entire surface of the resultant, and a flowing process is performed.
PMOS FET의 경우는 P형 기판(또는 P-Well)대신 N형 기판(또는 N-Well)과 n+소오스/드레인 이온주입 대신 P+소오스/드레인 이온주입을 수행하면 된다.In the case of the PMOS FET, P + source / drain ion implantation may be performed instead of n-type substrate (or N-Well) and n + source / drain ion implantation instead of the P-type substrate (or P-Well).
따라서 본 발명은 서브 미크론의 하이 덴시티(high density)를 갖는 집적회로로써 반복되는 구조인 게이트 어레이나 메모리등에 이용하면 아이솔레이션 영역감소에 따른 집적도 향상에 크게 기여할 수 있는 효과가 있다.Therefore, the present invention can greatly contribute to the improvement of the degree of integration due to the reduction of the isolation area when used in a gate array or a memory which is a repetitive structure as an integrated circuit having a high density of sub-micron.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019900016256A KR930008906B1 (en) | 1990-10-13 | 1990-10-13 | Isolation method of semiconductor device |
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| KR1019900016256A KR930008906B1 (en) | 1990-10-13 | 1990-10-13 | Isolation method of semiconductor device |
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| KR930008906B1 true KR930008906B1 (en) | 1993-09-16 |
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| KR100671155B1 (en) * | 2001-06-26 | 2007-01-17 | 매그나칩 반도체 유한회사 | Method for manufacturing an isolation layer in a semiconductor device |
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