KR930008804A - VRT's Bitrate Reduction Method and Its Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit rate reduction algorithm in digital BCs. Conventional image data compression techniques, which are generally used, list data to be coded in order of magnitude rather than probability of data to be coded and neighboring data. Find the probabilities by finding the difference between them, and then Huffman code this difference.

However, the above-described entropy coding, Hoffman coding, has been known as the most optimal coding technique. However, since this coding scheme removes only the probabilistic redundancy of the data to be processed, it is removed when any redundancy is inserted into the data to be processed. can not do. Coding schemes are also very vulnerable to errors, so they propagate to the next, usually catching blocks of any size to prevent the propagation of errors. Huffman coding is dependent on the input data and implies complexity and decoding difficulties in hardware implementation.

Accordingly, the present invention does not require a memory or a complicated decoder without investigating the statistical characteristics of the data, unlike Hoffman coding, in view of the combination of the conventional coding method as described above. The present invention provides a pre-bit array variable word length code, a method, and an apparatus for calculating and encoding a block, which are subjected to discrete cosine transform processing on a block-by-block basis, and then quantized and sequentially stored by zigzag scanning. The bit array mask encodes the bit after considering that the data after the previous data is the same or smaller than the previous data, and maintains a constant amount of data every frame and has great flexibility in realizing the multi-speed play mode. Error in time and time domain Since the block scramble processing is to have a strong characteristic to a burst error.

Description

VRT's Bitrate Reduction Method and Its Circuit

Since this is an open matter, no full text was included.

2 is a bit rate reduction circuit diagram of a digital VR of the present invention;

3 (a) and (b) shows the image data before and after the block scrambling process, and 4 (a), (b) and 5 (a) and (b) shows the feedback control variables according to the segment index. Interrelationship diagram.

Claims (5)

Frame memories 10 and 11, each of which is sampled at 13.5 MHz, 3.375 MHz, and 3.375 MHz to store digitized video signals with 8 bits for each sample data, and a scrambling unit 12 for randomizing an input image divided into blocks. 13), the DCT unit 14 for classifying the data spread in the spatial domain for each frequency, all coefficients below the threshold except for the DC coefficient are set to zero, and the coefficients over the threshold are extracted according to the threshold. A threshold determination section 15 to assign a weight to the coefficient of each AC component by the human visual system, and a step for each coefficient that changes according to the relative importance to the human visual system. A quantization unit 17 for quantization for size, a VLC unit 18 for performing coding by inserting a random pattern into data symbols to be coded, and performing coding using the same; Average bit desired to count the number of bits used in the treatment and non-matching buffer 19 and buffer controller 20 that is configured as a bit calibrated with the reduction of V CR, characterized in that circuit. Sample the input components (YUV) of the video signal at 13.5MHz, 3.375MHz, and 3.375MHz, respectively, and digitize them into 8 bits for each sample data, divide the input image into non-overlapping blocks, randomize them through the block scrambling process, and then Independently apply two-dimensional discrete cosine transform to the block, quantize only the threshold transform coefficients or more, and code the address value corresponding to the quantized data size into variable length (YWL) again. And then multiplexing it, thereby buffering the resulting bit stream to form a constant encoder output bit rate. The method according to claim 2, wherein the conversion coefficient is set to zero for all thresholds or less except DC coefficients in the threshold processing process, and the coefficients above the threshold value are reduced by the threshold value according to the human time system. And weighting the coefficients and quantizing them. 3. The variable length coding of claim 2, wherein the variable length coding is performed by sorting the quantized AC coefficients according to their absolute sizes, inserting an arbitrary pattern into the coding deal data symbols, and assigning redundancy to perform coding therefrom. Bitrate reduction method of digital VR using 5. The method of claim 4, wherein the sorting of the quantized AC coefficients is arranged such that the preceding coefficients are less than or equal to the latter coefficients. ※ Note: The disclosure is based on the initial application.