KR930006738B1 - Digital voltage controlled osillator - Google Patents

Abstract

The digital voltage controlled oscillator expands the output frequency range in a digital PLL or a digital servo mechanism. The digital VCO includes a counter (11) for counting the system clock (CLK), a latch (12) for latching the comparison imput (CV) in response to the load signal (LD), a comparator (13) for comparing the output (LV) of the latch with the output (SV) of the counter, two OR gates (OR11,OR12) for OR-ing the output (PO) of the gate (14) and the load signal (LD), a RS flip-flop (16) controlled by the outputs of OR gate (OR12) and a second counter (15), a phase/duty control circuit (17) for counting the system clock and comparing the count value with the rise/fall edge phase data, and a number of gates.

Description

Digital Voltage Controlled Oscillators

1a and b are conceptual diagrams of a general digital voltage controlled oscillator.

2A and 2B are integral and counter type configuration diagrams of a conventional digital voltage controlled oscillator.

3a to e are schematic timing diagrams of an integrated digital voltage controlled oscillator according to FIG. 2a.

4a to d are operational timing diagrams of the counter-type digital voltage controlled oscillator according to FIG. 2b.

5 is a block diagram of a digital voltage controlled oscillator according to the present invention.

6 is a detailed configuration diagram of a phase and duty ratio adjustment circuit according to FIG. 5;

7a to o are operational timing diagrams of the digital voltage controlled oscillator of the present invention according to FIG.

* Explanation of symbols for main parts of the drawings

11,17-1: counter 12: latch

13,17-2,17-3: comparator 14,15: gate

16,17-4: RS flip-flop 17: Phase and duty ratio control circuit

B11: Buffer CLK: System Clock

CV: Comparison input FALL: Falling edge phase information

I11: Inverter Gate LD: Load Signal

NA11: NAND Gate RISE: Rising Edge Phase Information

OR11, OR12: Oagate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital voltage controlled oscillator, and more particularly, to digital output voltage control that is suitable for improving the performance of a digital locked phase loop (PLL) device or a digital servo system with a simple hardware configuration. It's about an oscillator.

In general, a voltage controlled oscillator is a device for varying the frequency of an output signal as the magnitude of an input voltage, and is widely used in a broadcasting station or a rotation system control system. As shown in FIG. 2, an analog voltage controlled oscillator (VCO) 1, which receives an analog control voltage Va and controls an output frequency, receives a digital voltage control value Vd and outputs the analog voltage controlled oscillator 1. (Fout) There is a digital voltage controlled oscillator 2 that controls the frequency.

Conventionally, an analog voltage controlled oscillator (VCO) 1 has been generally used, but recently, a digital voltage controlled oscillator 2 has been used a lot due to the tendency of the system to be mostly digitalized.

2a and b show the configuration of the integral type and the counter type of the digital voltage controlled oscillator according to FIG. 1b. As shown therein, the integrated type and digital voltage controlled oscillator add the digital control signal Vd and the feedback value. An adder (3), a latch (4) which latches the output of the adder (3) in synchronization with the latch clock (LCK), feeds back to the adder (3), and transfers it to the next stage, and the latch (4). Comparator 5 which compares the output SV of the circuit and the comparison input CV to the next stage, outputs it as a clear signal of the latch 4, and the output of the comparator 5 And a phase and duty ratio adjustment circuit 6 which receives the EQ) and the phase and gain information PHD, and outputs the variable phase and duty ratio.

In addition, the counter-type digital voltage controlled oscillator includes a counter 7 which receives the system clock CLK as a counter input as shown in FIG. 2B, counts the output, and an output SV ′ of the counter 7 and a comparative output ( Comparing the CV) and outputting it as a reset signal of the counter 7 and outputting it to the next stage EQ ', the output EQ' of the comparator 5 and the phase and gain information ( PHD) and the phase and duty ratio adjustment circuit 6 for outputting by adjusting the phase and duty ratio (Fout).

The operation and problems of the conventional digital voltage controlled oscillator configured as described above are as follows.

3a to e are operation timing diagrams of the integral type digital voltage controlled oscillator of FIG. 2a. As shown in FIG. 3b, the latch voltage 4 is controlled by the latch clock LCK as shown in FIG. In this case, since the previous value SV and the current input Vd latched to the latch 4 are added by the adder 3 and input to the latch 4, each time the latch clock LUK rises. As shown in FIG. 3B, the latch output SV is increased in steps by the voltage control value Vd, and the latch output SV is compared with the comparison input CV in the comparator 5 so as to output the latch output SV. At this point, the comparator 5 performs the control output EQ and the latch 4 is cleared at a time point equal to or larger than the comparison input CV (CV <SV). Therefore, when the comparison input CV has the levels of a, b, and c in FIG. 3b, the output EQ of the comparator 5 pulses at the same timing as in FIG. 3c, d, and e. Since the output time of the comparator 5 changes according to the level of the input CV and the output EQ frequency of the comparator 5 changes, the phase and duty ratio adjustment circuit 6 outputs the output of the comparator 5. The frequency is adjusted to the phase and the duty ratio according to the phase and gain information (PHD) to achieve the final frequency output (Fout). Therefore, when the control voltage value Vd and the comparison output CV are varied, it is possible to vary the frequency of the output Fout.

4a to d are operation timing diagrams of the counter type digital voltage controlled oscillator according to FIG. 2b. As shown therein, the counter type of FIG. 2b is an integral latch 4 and adder 3 of FIG. 2a. Is replaced by the counter 7, the counter 7 counts the system clock CLK as shown in FIG. 4a and increases the count value SV as shown in FIG. 4b. In the comparator 5, the comparison input CV When the coefficient value SV is increased in comparison with the, the comparator 5 compares the comparison input CV with the comparator 5 and the first time point when the coefficient value SV is equal to or larger than the comparison input CV (SV> CV). Since the comparator 5 makes a control output at, the output timing of the comparator 5 is changed as shown in 4c and d when the level of the comparison input CV is a ', b' so that the counter 7 In addition to being cleared, it is input to the phase and duty ratio adjustment ratio (6). That is, the frequency of the output EQ of the comparator 5 is variable according to the change of the comparison input CV, and the phase and duty ratio of the output EQ of the comparator 5 is changed according to the phase and gain information PHD. To adjust the frequency output (Fout).

However, such a conventional integrated voltage controlled oscillator must have a high frequency of the latch clock LCK in order to increase the resolution of the output frequency, and the latch 4 will have a high value when the value of the control voltage value Vd is large. It is disadvantageous to output low frequency because it reaches the maximum value which can be reached as soon as possible. Even if you want to improve the resolution of output frequency by increasing the latch clock (LCK), the latch (4) reaches the maximum value at the same time as soon as possible. The adjustment range of the frequency Fout becomes narrow.

In addition, the counter-type voltage controlled oscillator can output a frequency having the same resolution as that of the system clock CLK supplied to the counter 7, which is advantageous in terms of resolution rather than the integral type, but the counter 7 can count. The lower limit of the oscillation frequency is determined by the maximum possible value and the time required. In other words, if the counter 7 is an n-bit counter, the lowest frequency of the output is 1 / Tmax ( ^where Tmax is the time required to count (2 ⁿ -1)). On the other hand, the maximum frequency that can be output can not exceed the input system clock (CLK).

In view of the above problems, the present invention is advantageous in extending the range of the oscillation frequency by selecting the counter of the maximum number of bits using the digital digital voltage controlled oscillator, so that when the counter having the maximum number of bits has only n bits or the gate array. In the case of implementing an integrated device in the form of a digital voltage controlled oscillator which can extend the range of the output oscillation frequency to twice the range of the conventional structure with a simple configuration when the maximum number of bits is limited to n bits. Detailed description with reference to the following.

5 is a configuration diagram of a digital voltage controlled oscillator according to the present invention, and as shown therein, a counter 11 for counting the system clock CLK and a comparison input CV are latched according to the load signal LD. A comparator 13 for comparing the latch 12, the n-bit output LV excluding the most significant bit MSB output of the latch 12, and the n-bit output SV of the counter 11, and the comparator First, second gates 14 and 15 and the load signal LD and the first gate 14 which output the output EQ of the signal 13 to the next stage according to the enable control signal EN. The OR signals OR11 and OR12 that combine the outputs PO) and the outputs of the OR gate OR12 are input as a set signal S, and the outputs of the second gate 15 are reset signals. RS flip-flop 16 which is inputted to (R) and outputs control, and the output of the RS flip-flop 16 is applied as one input through buffer B11 and outputs the most significant bit MSB of the latch 12. The other side A NAND that is inputted as an input and applied as an enable signal EN of the gate 14 as well as an enable signal EN2 of the second gate 15 through an inverter gate I11. The system clock CLK is counted by applying the gate NA11 and the output PO of the first gate 14 as a clear signal, and the counted value is a rising edge from a system controller (not shown). And a phase and duty ratio adjustment circuit 17 which compares the phase information signal RISE and the falling edge phase information signal FALL and performs an output Fout set / reset in accordance with the comparison value.

FIG. 6 is a detailed configuration diagram of the phase and duty ratio control circuit according to FIG. 5. As shown in FIG. 6, the system clock CLK is counted by receiving the output PO of the first gate 14 as a clear signal. First and second comparators 17-2 for comparing the counter 17-1, the output of the counter 17-1, and the rising edge phase information RISE and the falling edge phase information FALL of the system controller, respectively. ), (17-3) and the outputs of the first and second comparators 17-2 and (17-3) as the set signal S and the reset signal R, respectively, and the oscillation frequency output ( RS flip-flop 17-4 which performs Fout).

Here, the output of the OR gate OR11 of FIG. 5 is input as a clear signal of the counter 11, and the system clock CLK, the load signal LD, and the comparison input CV are input from a system controller (not shown). And phase information signals RISE and FALL are input to the digital voltage controlled oscillator of the present invention.

The operation and effect of the present invention configured as described above will be described in detail with reference to the operation timing diagrams of FIGS. 5 and 6 according to FIGS.

In the digital voltage controlled oscillator of FIG. 5, when the counter 11 continuously counts the system clock CLK as shown in FIG. 7c, the load signal LD as shown in FIG. 7a and FIG. When input, the latch 12 represented by (n + 1) bits latches the comparison input CV to input the output LV of n bits excluding the most significant bit MSB to the comparator 13, and at this time, the load signal LD is inputted as a clear signal of the counter 11 and a set signal S of the RS flip-flop 16 through the OR gates OR11 and OR12, so that the counter 11 receives the load signal LD. The system clock CLK starts counting from the time point after the input, and the RS flip-flop 16 outputs a high potential signal by inputting the set signal S according to the load signal LD to generate the buffer B11. It is input to the NAND gate NA11 through. Meanwhile, in the latch 12, the value of the most significant bit MSB is determined according to the input value CV.

MSB = 0; However, when 0 <CV≤ (2 ⁿ -1)

MSB = 1; However, when 2 ⁿ ≤ CV ≤ (2 ^{n + 1} -1)

Therefore, when the most significant bit MSB of the latch 12 is the low potential MSB = 0, the output of the NAND gate NA11 enables the first gate 14 as a high potential ("1") signal ( EN1), and when the most significant bit (MSB) is high potential (MSB = 1), the output of the NAND gate NA11 is a low potential ("0") signal and is inverted through the inverter gate I11 and converted into a high potential signal. The second gate 15 is enabled EN2.

In this state, the output value SV of the counter 11 as shown in FIG. 7d in which the counter 11 counts the system clock CLK after the load signal LD is equal to the comparison input CV stored in the latch 12. The ground comparator 13 outputs a pulse at the same timing as that of Fig. 7e, where the timing (a) shown in Figs. 7a to g when the comparison input CV is in the state of 0 <CV≤ (2 ⁿ -1). In this case, the output of the most significant bit MSB of the latch 12 is the low potential (MSB = 0), and the output of the NAND gate NA11 is a high potential signal such as the seventh degree, so that the first gate 14 is enabled ( In the state of EN1, the output PO of the first gate 14 is a timing pulse signal similar to the 7e diagram of the comparator 13 as shown in FIG. 7g, and the counter 11 is cleared through the oragate OR11. To start counting again.

That is, in the case of (a) ^where 0 <CV ≤ (2 ⁿ -1) in FIG. 7, the counter 11 outputs the output of the comparator 13 when the system clock CLK is counted by the data value of the comparison input CV. The counter 11 is inputted to the phase and duty ratio control circuit 17 through the first gate 14 and the counter 11 is cleared again through the ORA gate OR11, so that the counter 11 receives the comparison input CV. It counts by period and outputs the pulse according to the period to the phase and duty ratio adjustment circuit 17. FIG.

In the case of (a) to (ka) in FIG. 7b in which the comparison input CV is 2 ⁿ ≤ CV ≤ (2 ^{n + 1} -1), the most significant bit of the latch 4 according to the comparison input CV Since the output of the MSB becomes high potential (MSB = 1), the output of the NAND gate NA11 is inverted through the inverter gate I11 as a low potential signal to enable the second gate 15 EN2.

Therefore, the latch 12 latches the comparison input CV with the load signal LD as shown in FIG. 7i and starts counting the counter 11 and the system clock CLK, and counts n bits of the counter 11. When the value SV becomes equal to the n bit value among the n + 1 bits of the comparison input CV latched in the latch 12 after the predetermined time t, the comparator 13 causes the pulse output EQ. In this case, since the first gate 14 is in a disabled state, the output of the first gate 14 is lost, and the counter 11 continues to count the system clock CLK again. The output pulse EQ resets the RS flip-flop 16 through the second gate 15 in the enabled state so that the RS flip-flop 16 outputs a low potential. When the RS flip-flop 16 outputs a low potential, the NFL gate NA11 is applied to one side of the NAND gate NA11 through the buffer B11 so that the NAND gate NA11 outputs a high potential signal. 14 is enabled and the second gate 14 is disabled so that the next pulse of the comparator 13 can be output through the first gate 14. In this state, the counter 11 counts the first n-bits and then n + 1 of the comparison input CV stored in the latch 12 with the n-bit count value SV counted after a predetermined time T again. When the value equals to the n bit value among the bits, the comparator 13 generates a pulse output EQ, which is output to the phase and duty ratio control circuit 17 through the first gate 14 in the enabled state. At the same time, the counter 11 is cleared through the OR gates OR 11 and OR 12, respectively, and the RS flip-flop 16 is set. Here, the time taken when the comparator 13 shown in FIG. 7j counts t + T in the output pulse t + T: CV with a counter having (n + 1) bits.

t: time taken to count CV-2 ⁿ values.

T: Time taken to count 2 ⁿ values.

For example, when the counter 11 is a 3-bit counter, when the comparison input CV is latched to the latch 12 with the 4-bit signal "13 = 1101", the counter 11 returns "101" at the first count. At the time of counting, the comparator 13 outputs a pulse, but at this time, when the first gate 14 is in a disabled state and the counter 11 is not cleared, the counter 11 continues to count and becomes → 111 → 000 → 001 → 101. ) Pulses again to clear the counter 11 through the enabled first gate 14, sets the RS flip-flop 16, and controls the phase and duty ratio adjustment circuit 17. The 4-bit data ("134 = 1101") stored in the latch 12 is initially output by the 3-bit count of the counter 11 for CV-2 ⁿ = 13-2 ^a = 5 (= The comparator 13 outputs the first pulse by counting 101 and accordingly, the RS flip-flop 16 is reset so that the first gate 14 through the NAND gate NA11 is counted. ) To the enabled state.

At this time, since the buffer B11 has a predetermined delay timing, the primary pulse is prevented from passing through the first gate 14.

And so the count to "5 = 101" counted after by the counter 11 is not cleared to continue the count of "101 → 110 → 111 → 000 → 001 → 101" to time t1, during which time (T) 2 ⁿ = Counting " 8 " yields CV = 13 with CV-2 ⁿ +2 ⁿ = 5 + 8 = 13, resulting in counting the desired (n + 1) bit value.

On the other hand, the phase and duty ratio adjustment circuit 17 is clear-controlled according to the pulse signal PO input through the first gate 14 as shown in FIG. 6, and counts the system clock CLK. Count in 1). That is, as shown in the waveform diagrams of m to o shown in FIG. 7c, the system clock CLK is counted by the counter 17-1 by the output pulse PO of the first gate 14 of FIG. 7m. When counted together, the first comparator 17-2 and the second comparator 17-3 are compared with the phase information RISE and FALL signals output from the system controller.

When the count value of the counter 17-1 reaches the rising edge information RISE, the first comparator 17-2 performs the control output and sets the RS flip-flop 17-4 to set the oscillation output. (Fout) is output as a high potential signal with the rising edge, and when the count output of the counter (17-1) reaches the falling edge phase information (FALL), the second comparator (17-3) performs a control output The RS flip-flop 17-4 is reset R to output the oscillation output Fout as a low potential signal with a falling edge. Therefore, the oscillation output Fout is output as a frequency signal as shown in FIG. 7, which is used to output the rising and falling edge information RISE and FALL to the comparison input CV output through the first gate 14. The phase duty ratio of the oscillation output Fout can be adjusted within the control period, and the comparison input CV can be set to a CV value of n + 1 bits even if the counter 11 is an n-bit counter. .

As described above, the present invention makes it possible to provide an output frequency range that is twice as large as that of a voltage controlled oscillator using a counter of the maximum number of bits available when configuring a digitally controlled oscillator as a circuit or implementing an integrated element in a gate array method. In addition, the relatively simple hardware configuration can be used to improve the performance of a digital broadcasting station or a rotation control system of a motor used in a disc player.

Claims (2)

Counter 11 for counting n bits of system clock CLK, n + 1 bit latch 12 for latching comparison input CV by load signal LD, and most significant bit of latch 12. The comparator 13 for comparing the output LV except for the count output SV of the counter 11 and the pulse output EQ of the comparator 13 with the enable signals EN ₁ and ( The counter 11 by combining the first and second gates 14 and 15 passed by EN ₂ , the output PO of the first gate 14, and the load signal LD. of the Iowa gate (OR ₁₁₎ to be applied to the clear signal, the first output and Iowa gate (OR _12), which Iowa combining the load signal (LD) of the gate 14, the Iowa gate (OR ₁₂₎ An RS flip-flop 16 subjected to set and reset control by an output and an output of the second counter 15, a buffer B ₁₁ buffering an output of the RS flip-flop 16, and the buffer ( B ₁₁₎ of the output and the The output of the most significant bit (MSB) NAND gates (NA ₁₁₎ and said NAND gate (NA ₁₁₎ for applying to the output of NAND combination of the enable signal (EN ₁₎ of the first gate 14 of the latch 12 Is inverted and is cleared by the inverter gate I ₁₁ applied to the enable signal EN ₂ of the second gate 15 and the output PO of the first gate 14, and the system clock CLK. ) And a phase and duty ratio control circuit 17 for oscillating output Fout by comparing the count value with rising / falling edge phase information RISE and FALL. Voltage controlled oscillator. The phase duty ratio adjustment circuit 17 is a counter 17-1 which is clear controlled by the output PO of the first gate 14 and counts the system clock CLK. Comparing whether the output of the 17-1) is equal to the rising edge phase information (RISE) and whether the output of the counter 17-1 is the same as the falling edge phase information (FALL) RS flip-flop which is set by the second comparator 17-3 and the outputs of the first, second comparators 17-2, 17-3 and receives the oscillation output Fout under reset and reset control. Digital voltage controlled oscillator, characterized in that consisting of (17-4).