KR930005816B1

KR930005816B1 - Circuit generating parallel syncro signal

Info

Publication number: KR930005816B1
Application number: KR1019900022489A
Authority: KR
Inventors: 홍순양; 이준성; 김용현; 박의근
Original assignee: 삼성전자 주식회사; 김광호
Priority date: 1990-12-29
Filing date: 1990-12-29
Publication date: 1993-06-25
Also published as: KR920013419A

Abstract

The generator circuit for a video signal processing system uses minimum digital logic units to reduce the chip size. The generator circuit comprises an eight digit counter (C) for recieving and counting a chrominance signal and including D flip-flops and a T flip-flop, a time setting counter (T) for receiving the counter (C) output signal to stop and perform the counting according to the states of T flip-flops (T F/F2 - T F/F6), a wave setforming circuit (P) for receiving a chrominance pulse from the counter (T) and a complex sync. signal of the video signal to output a horizontal sync. signal by using the time constant of gate and capacitor.

Description

Horizontal Synchronous Signal Generation Circuit Using Waveform Shaping Circuit

제1도는 본 발명 파형정형회로를 이용한 수평동기신호 발생회로의 블럭도.1 is a block diagram of a horizontal synchronous signal generating circuit using the waveform shaping circuit of the present invention.

제2a 내지 f도는 파형정형 펄스신호도.2a to f are waveform shaped pulse signal diagrams.

제3a 내지 d도는 8진 카운터 플립플롭 펄스신호도.3a to d are octal counter flip-flop pulse signal diagrams.

제4a 내지 f도는 시간설정카운터부의 카운트 신호도.4A to 4F are count signal diagrams of the time setting counter unit.

제5a 내지 f도는 제4도의 신호를 상세히 표시한 신호도.5a to f are signal diagrams showing in detail the signal of FIG.

제6a 내지 g도는 제2도와 제5도의 신호를 조합한 최종출력신호도.6a to g are final output signal diagrams combining the signals of FIG.

본 발명은 VTR등의 영상신호처리시스템에 관한 것으로서, 특히 수직 블랭킹(blanking)기간에도 수평동기신호와 같은 펄스를 발생하여 화면을 안정시키는 파형정형회로를 이용한 수평동기신호 발생회로에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing system such as a VTR, and more particularly, to a horizontal synchronous signal generating circuit using a waveform shaping circuit that stabilizes a screen by generating a pulse such as a horizontal synchronous signal even during a vertical blanking period.

종래의 수평동기신호 발생회로는 아날로그로 구성되어 있어 소자수가 많으므로 칩 사이즈가 크게 되어 집적화가 어려운 문제점이 있었다.The conventional horizontal synchronous signal generating circuit is composed of analog, so the number of devices has a large chip size has a problem that is difficult to integrate.

따라서 본 발명은 수평동기신호를 발생하는데 필요한 로직(Logic)을 최소화하여 디지털화 시킴으로써 칩 사이즈를 줄여 그 적용범위를 넓힐 수 있는 수평동기신호 발생회로를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a horizontal synchronous signal generating circuit which can reduce the chip size and widen its application range by minimizing and digitizing logic required to generate a horizontal synchronous signal.

상기 목적을 수행하기 위한 본 발명은 카운터 역할을 하는 D와 T 플립플롭(Flip Flop), 낸드게이트(Nand Gate)들로 구성된 랫치(Latch), 그리고 지연(Delay)을 발생시키기 위한 캐패시터등으로 구성된 것을 특징으로 한다.The present invention for carrying out the above object is composed of a D and T flip-flop (Lip) that acts as a counter, a latch composed of Nand Gates, and a capacitor for generating a delay, etc. It is characterized by.

이하 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, described in detail with reference to the accompanying drawings.

제1도는 파형정형회로를 이용하여 수평동기신호를 출력하는 본 발명에 따른 블럭도로서 입력(1,2)는 각각 복합동기신호와 색신호로, 입력(1)은 이 블럭도에서 출력되어지는 수평동기신호를 발생시키기 위한 영상신호이며, 입력(2)는 약 3.58MHz의 색신호 주파수로써 입력(1)의 복합동기신호중에서 수평동기신호만을 출력하도록 컨트롤 하기 위한 카운터부(C)의 입력신호가 된다.1 is a block diagram according to the present invention for outputting a horizontal synchronous signal using a waveform shaping circuit, wherein inputs 1 and 2 are complex synchronous signals and color signals, respectively, and input 1 is output horizontally in this block diagram. It is an image signal for generating a synchronization signal, and the input 2 is an input signal of the counter unit C for controlling to output only a horizontal synchronization signal among the composite synchronization signals of the input 1 at a color signal frequency of about 3.58 MHz. .

본 발명은 카운터 역할을 하는 플립플롭(Flip Flop)와 낸드게이트(Nand Gate)들로 구성된 랫치(Latch), 딜레이를 발생시키는 캐패시터(C₁)등으로 구성되어져 있으며 제2도에서와 같은 영상신호의 합성동기펄스신호(a)를 입력받아 낸드게이트(N₁)의 출력파형(c)을 두부분으로 나누어지게 함으로써 캐패시터(C₁)의 시정수만큼 딜레이를 갖고 출력되어지는 인버터(I₃)의 출력신호와, 원래의 낸드게이트(N₁) 출력신호를 낸드게이트를 이용하여 낸드게이트(N₂)의 출력파형(f)를 발생시키는 회로를 파형정형회로(P)라 한다.The present invention consists of a latch consisting of a flip flop and a Nand gate serving as a counter, a capacitor C ₁ generating a delay, and the like, as shown in FIG. The output waveform c of the NAND gate N ₁ is divided into two parts by receiving the synthesized synchronizing pulse signal a of the input signal of the inverter I ₃ outputted with the delay as much as the time constant of the capacitor C ₁ . A circuit for generating the output waveform f of the NAND gate N ₂ using the output signal and the original NAND gate N ₁ output signal using the NAND gate is called a waveform shaping circuit P. FIG.

8진카운터부(C)는 제3도의 색신호주파수(3.58MHz)펄스(a)를 입력받아 T 플립플롭과 D 플립플롭에서 각각 펄스(b), (c), (d)와 같이 8진 카운터하여 입력되는 색신호의 시간에러를 줄여 출력시키게 된다. 시간설정카운터부(T)는 색신호를 8진 카운터한 제3도의 출력신호를 입력받으면 제4도 각부의 파형도에서와 같이 일정시간 후 리셋이 걸려서 플립플롭이 동작하지 못하도록 일정시간 동안 카운트를 멈추게 되며, T 플립플롭(T F/F₂~T F/F₆)이 모두 하이(high)일 경우 낸드게이트(N4)는 로(low)신호를 발생시키게 되고 낸드게이트(N₅)의 두 입력 하이(high)일때 리셋이 풀리게 되고 그 출력은 그 로(low)가 되어 인버터(I₃,I₄)를 거쳐 플립플롭들의 리셋이 풀리게 되어 카운트를 하게 된다.The octal counter unit C receives the color signal frequency (3.58 MHz) pulse a of FIG. 3 and outputs an octal counter such as pulses (b), (c), and (d) in the T flip-flop and the D flip-flop, respectively. By reducing the time error of the input color signal is output. When the time setting counter part T receives the output signal of FIG. 3 which has an octal counter of the color signal, the counter is reset after a certain time as shown in the waveform diagram of each part of FIG. When the T flip-flops TF / F ₂ to TF / F ₆ are all high, the NAND gate N4 generates a low signal and the two input high NAND gates N ₅ are generated. high, the reset is released and its output goes low, causing the flip-flops to be reset through the inverters I ₃ and I ₄ to be counted.

제6도는 복합동기펄스신호(a)를 입력받아 최종출력신호인 수평동기펄스신호(g)를 출력하는 펄스신호도이다.6 is a pulse signal diagram for receiving a composite synchronous pulse signal a and outputting a horizontal synchronous pulse signal g which is a final output signal.

즉, 본 발명은 복합동기펄스신호(a)중에 수평동기신호만을 출력하도록 컨트롤 하기 위한 카운터 역할을 하는 색신호(입력 : 2)는 8진 카운터부와 시간설정카운터부를 거치며, 복합동기신호(입력 : 1)는 이 신호와 파형정형회로를 통해 얻어진 출력을 입력으로 하여 원하는 수평동기신호를 발생시키게 된다.That is, in the present invention, the color signal (input: 2) serving as a counter for controlling to output only the horizontal synchronizing signal among the complex synchronizing pulse signals (a) passes through an octal counter part and a time setting counter part, and a complex synchronizing signal (input: 1) inputs this signal and the output obtained through the waveform shaping circuit to generate a desired horizontal synchronizing signal.

본 발명은 종래 아날로그회로를 디지탈화하여 칩 사이즈를 줄일 수 있으며 VTR, 캠코더, TV등 수평동기신호를 필요로 하는 모든 부분에 이용될 수 있다.The present invention can reduce the chip size by digitalizing a conventional analog circuit and can be used for all parts requiring horizontal synchronization signals such as a VTR, a camcorder, and a TV.

Claims

An octal counter part (C) consisting of a D flip-flop and a T flip-flop that inputs a color signal as an input, and an octal counter-output signal is input, resets after a predetermined time, and stops the flip-flop operation. NAND gate (N ₄ ) generates a low signal only when both the T flip-flops (TF / F ₂ to TF / F ₆ ) are high and reset occurs when both inputs of NAND gate (N ₅ ) are high. Unlocked flip-flops are operated to counter the time setting counter (T), which receives the mixed synchronous signal of the color signal pulse and the video signal from the time setting counter, and outputs the horizontal synchronous signal using the time constant of the gate and the capacitor. A horizontal synchronous signal generating circuit using a waveform shaping circuit, characterized in that it comprises a waveform shaping circuit (P).

The method of claim 1, wherein the waveform shaping circuit (P) is a feed back the output signal of the horizontal sync signal receives the composite synchronizing signal into the input (1) (feedback) inverter (I _2), the input composite synchronizing signal to the inverter ( I ₂₎ capacitors which are logically as NAND (Nand) the signal is output generating the NAND gate (N _1), an inverter (I ₁₎ of the output of the NAND gate (N ₁₎ and the delay is (C ₁₎ NAND gate (N ₂ ) and NAND gate (N ₂ ) in which a signal in which the output of the NAND gate (N ₁ ) is delayed by the inverter (I ₁ ) signal and the capacitor (C ₁ ) is input, and a signal which is logically NAND is outputted. ₂ ) Low signal when the output signals of NAND gate (N ₃ ) and flip-flop (TF / F ₂ ~ TF / F ₆ ), which generate the horizontal synchronous signal by inputting the signals of NAND gate (N ₅ ), finally When NAND gate (N ₄ ), NAND gate (N ₄ ) and NAND gate (N ₃ ) output signals are systematically output to NAND The key is a horizontal synchronous signal generation circuit using a waveform shaping circuit, characterized in that consisting of (N ₅ ).