KR930005603B1 - Teletext data detecting circuit - Google Patents

Abstract

The circuit generates the reference level prevented from being varied by detecting peak level with a differential amplifier to improve the characteristics of teletext data abstracting. The circuit includes a differential amplifier section (11a) for detecting positive signal from input signal (Vin), an emitter follower outputting sect. (11b) for negatively feeding back level stabilizing output (VL) and peak level output (VH) to differential amplifier sect. (11a,12a), and an averaging circuit (13) for generating the reference level signal (Vref) of teletext data abstracting.

Description

Teletext data extraction reference level generator

1 (a) and (b) are schematic diagrams of a teletext data signal.

2 is a block diagram of a typical teletext data extraction system.

3 is a conventional teletext data extraction reference level generation circuit diagram.

4 is a schematic diagram of a teletext data extraction reference level generation circuit according to the present invention.

5 is a signal waveform diagram of each part for explaining the present invention.

* Explanation of symbols for main parts of the drawings

11: high peak level detector 12: low peak level detector

11a: positive detection differential amplifier 12a: negative detection differential amplifier

11b, 12b: emitter follower output stage 13: average circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference level generator for extracting teletext data, and more particularly, to a reference text generator for extracting a level of text due to variation of device variables.

The general teletext data includes a color burst signal (C), two bytes of clock synchronization signal (CS), one byte of byte in one horizontal synchronization signal (H), as shown in FIGS. 1A and 1B. It consists of a synchronization signal BS and teletext data TXT. That is, as shown in (b), the teletext data TXT is input after the 16-bit clock synchronization signal CS and the 8-bit byte synchronization signal BS.

2 is a block diagram of a general teletext data extraction circuit. As shown in FIG. 2, a composite image signal is input through a buffer 1, and a reference level generator 2 detects a clock synchronization signal CS. Sampled and held in (3), the output of the buffer 1 is compared by the comparator 4 based on this sampling value, and the teletext digital data TXT superimposed on the composite video signal is extracted.

The average value of the clock synchronizing signal CS of the composite video signal inputted from the reference level generator 2 is detected.

In the conventional reference level generating circuit, as shown in FIG. 3, the input signal Vin, which receives the composite image signal through the buffer 1, receives the input signal Vin of the low peak level detector 2a. The low pickle level V _L is detected through the capacitor C _L connected to the collector of the QP2, QP3 and the PNP transistor QP2, and the input signal Vin is converted into a high peak level. The high peak level V _H is set through the high peak level detection unit 2b through the NCP transistors Qn1, Qn2 and Qn3, and the capacitor C _H connected to the collector of the ENP transistor Qn2. After detecting and calculating the average values of the low peak level (V _L ) and the high peak level (V _H ) through the resistors R1 and R2 of the average circuit 2c, respectively, the reference level signal Vref through the buffer B1. Will be printed.

(V_L+V_H)가 되어 이 평균값인 기준레벨신호(Vref)가 샘플/홀더(3)에서 홀딩하여 비교기(4)의 기준값으로 인가하게 된다.The average value of the average circuit 2c is

The reference level signal Vref, which is this average value, is held at the sample / holder 3 and applied as the reference value of the comparator 4 by (V _L + V _H ).

(3V_BE.P)-3V_BE.N)

+ (V_InL+V_InH)가 된다(단 V_BE.P및 V_BE.N은 PNP 및 NPN트랜지스터의 베이스-에미터간 전압).However, the reference level signal Vref, which is the output of the reference level generating circuit, has Vref =

(3V _BE.P ) -3V _BE.N )

+ (V _InL + V _InH ), where V _BE.P and V _BE.N are the base-emitter voltages of the PNP and NPN transistors.

Therefore, if V _BE.P and V _BE.n , which are process variables, do not coincide with each other, the reference voltage Vref may fluctuate and deteriorate the teletext (TXT) data extraction characteristic.

In consideration of such a deficiency, the present invention has been made a reference level generating circuit which prevents the variation of the reference voltage (Vref) according to the process variable by using a peak amplifier for the peak level detection, in detail with reference to the accompanying drawings. The explanation is as follows. Differential instantaneous stage 11a in which the collectors of the active load current mirror PNP transistors Q13 and Q14 are connected to the respective collectors of the differential NPI transistors Q11 and Q12 connected to the current source CS1 by the emitter in common. The input signal Vin is applied to the base of the ENP transistor Q11, and the emitter of the ENP transistor Q15 is applied to the base of the high peak level detection capacitor C _H and the ENP transistor Q16. The emitter follower output terminal 11b connected to an emitter of the ENP transistor Q16 connected to the base of the ENP transistor Q12 which is a negative feedback input terminal of the current source CS2 and the differential amplifier terminal 11a. The collector output of the ENP transistor Q12, which is the output of the differential amplifier stage 11a, is applied to the base of the ENP transistor Q15 so that the emitter output of the ENP transistor Q16, which is the negative connection point, is set at a high peak level ( Hi-fi with V _H ) output The current level CS3 is connected to the surge level detecting unit 11 and the common emitter, and the collectors of the differential PNP transistors Q21 and Q22 are connected to the active load current mirror NP transistors Q23 and Q24. The input signal Vin is applied to the base of the PNP transistor Q21 of the differential amplifier stage 12a connected to the collector, and the emitter of the PNP transistor Q25 is connected to the low peak level detection capacitor C _L and the P peak. The emitter follower output terminal 12b connected to the base of the N-P transistor Q26 and connected to the base of the PNP transistor Q22, which is its emitter, is connected to the current source CS4 and the negative feedback input terminal 12a of the differential amplifier stage 12a. The output of the PNP transistor Q22, which is the output of the differential amplifier stage 12a, is applied to the base of the PNP transistor Q25 so that the emitter output is applied at a low peak level (PNP transistor Q26). V _L) to the output low blood Cradles The outputs of the detector 12, the high peak level detector 11 and the low peak level detector 12 are respectively applied through the resistors R1 and R2, and the average value is commonly obtained through the buffer B1. It consists of the average circuit 13 which makes a detection output Vref.

The operation and effects of the present invention configured as described above will be described with reference to the signal waveform diagram of each part according to FIG. 5 according to the present invention.

When the image signal input Vin is applied, the high peak level detector 11 detects the high peak level V _H of the input signal Vin, and the low peak level detector 12 detects the low of the input signal Vin. The peak level V _L is detected.

First, when the input signal Vin increases by more than the current high peak level output V _H , (Vin &_gt; V _H ), the differential amplifier stage 11a of the high peak level detection unit 11a, the ENP transistor Q11 and the peak The N-P transistors Q13 and Q14 are turned on so that the collector current of the P-P transistor Q14 flows into the base of the N-P transistor Q15 of the emitter follower output terminal 11b. C _H) while charging & P yen is output as & P ¥ Sikkim feedback to the base of the transistor (Q12) of said differential amplifier stage (11a) via a transistor (Q16) as well as in other words, the input signal (Vin) and the output (V _H) Until this equals (Vin = V _H ), the capacitor (C _H ) is charged.

Second, when the input signal Vin decreases below the high peak level output V _H , the NP transistor Q11, the PN transistors Q13, and Q14 are turned off, and the NP transistor Q12 is turned on. In this state, the emitter output V _H of the ENP transistor Q16 of the output terminal 11b is fed back to the current source CS1 so that a current flows between the base-emitter of the ENP transistor Q12.

Since the output stage 11b and the ENP transistor Q15 are turned off by turning the PNP transistor Q14 off, the capacitor C _H does not charge, but maintains its charging potential and maintains the base bias of the ENP transistor Q16. Supply. Therefore, the high peak level output (V _H ) remains in the holding state.

Here, the discharge potential of the condenser C _H is affected by the base current of the NP transistor Q16, but is negatively fed back to operate the differential amplifier stage 11a again, and the currents of the current sources CS1 and CS2 are supplied. It can be minimized by setting appropriately.

Third, when the input signal Vin is reduced below the low peak level V _L , the differential amplifier stage 12a PNP transistor Q21 and the ENP transistor of the low peak level detection unit 12 are applied at Vin <V _L. Q23 and Q24 are turned on, and the PNP transistor Q25 of the output terminal 12b is turned on in accordance with the turn-on of the ENP transistor Q24, so that the capacitor C _L turns the input signal Vin and the low peak level. When (V _L ) is the same, it is charged up to (Vin = V _L ), and accordingly, the base current of the PNP transistor Q26 is increased to decrease the low peak level (V _L ). Fourth, when the input signal Vin increases above the low peak level V _L , the PNP transistor Q21, the ENP transistors Q23 and Q24 are turned off, and the PNP transistor Q25 is turned on. In the off state, the charge loop of the capacitor C _L is cut off, and the base current of the PNP transistor Q26 is maintained by the capacitor C _L so that the low peak level V _L output is maintained. Here, the discharge loop of the capacitor C _L is maintained in the same process as the high peak level holding capacitor C _H.

As such, the high peak level V _H and the low peak level V _L detected by the high peak level detector 11 and the low peak level detector 12 are summed through the resistors R1 and R2, respectively, and averaged. The output Vref is output through the buffer B1 to the level Vref1.

This output (Vref) is sampled and held and compares with the video signal as a reference value to detect the teletext data.

As described above, the present invention detects the high / low peak level detection through a differential amplifier, maintains the level through the capacitor, and negatively determines the variation value. It is possible to obtain a stable reference level value by preventing the variation of the reference level value irrespective of the V _BE ) difference between the NPN and the PNP, thereby stably extracting the teletext data signal.

Claims (1)

Receive the composite video signal as the input signal (Vin), detect the high peak level (V _H ) and the low peak level (V _L ), average them, and extract the tele text data outputting as the teletext data extraction reference level (Vref). In the reference level generating circuit, capacitors C _H and C according to the outputs of the differential amplifier stage 11a that receives the input signal Vin and detects the positive signal and the differential amplifier stage 12a that detects the negative signal. _L ) maintains the level and the high peaks of the emitter follower output stages 11b and 12b for negative feedback of the respective peak level outputs V _H and V _L to the differential amplifier stages 11a and 12a, respectively. Teletext configured to sum up the level output V _H and the low pickle level output V _L through an average circuit 13, and output the average value as the teletext data extraction reference level signal Vref. Data extraction reference level generation circuit.

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