KR930005395U - D-RAM control circuit - Google Patents

D-RAM control circuit

Info

Publication number
KR930005395U
KR930005395U KR2019910012904U KR910012904U KR930005395U KR 930005395 U KR930005395 U KR 930005395U KR 2019910012904 U KR2019910012904 U KR 2019910012904U KR 910012904 U KR910012904 U KR 910012904U KR 930005395 U KR930005395 U KR 930005395U
Authority
KR
South Korea
Prior art keywords
control circuit
ram control
ram
circuit
control
Prior art date
Application number
KR2019910012904U
Other languages
Korean (ko)
Other versions
KR940005397Y1 (en
Inventor
박판기
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019910012904U priority Critical patent/KR940005397Y1/en
Publication of KR930005395U publication Critical patent/KR930005395U/en
Application granted granted Critical
Publication of KR940005397Y1 publication Critical patent/KR940005397Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Dram (AREA)
KR2019910012904U 1991-08-14 1991-08-14 Dram controller KR940005397Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910012904U KR940005397Y1 (en) 1991-08-14 1991-08-14 Dram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910012904U KR940005397Y1 (en) 1991-08-14 1991-08-14 Dram controller

Publications (2)

Publication Number Publication Date
KR930005395U true KR930005395U (en) 1993-03-22
KR940005397Y1 KR940005397Y1 (en) 1994-08-10

Family

ID=19317858

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910012904U KR940005397Y1 (en) 1991-08-14 1991-08-14 Dram controller

Country Status (1)

Country Link
KR (1) KR940005397Y1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190098890A (en) 2018-02-14 2019-08-23 정수현 Vessel enhancing structure and material of hull
KR102442542B1 (en) 2021-03-31 2022-09-08 목포해양대학교 산학협력단 Smart rescue boat

Also Published As

Publication number Publication date
KR940005397Y1 (en) 1994-08-10

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20030730

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee