KR930004527Y1 - Signal processing circuit for video recording/reproducing device - Google Patents

Abstract

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Description

Signal Processing Control Circuit of Image Recording Device

1 is a reference diagram of a switch circuit for generating a channel mode voltage in a conventional video recording (recording and playback) apparatus.

2 is a reference diagram of a selection circuit according to the dap recording time in the conventional video recording apparatus.

3 is a system block diagram of a signal processing control circuit according to the present invention.

4 is an embodiment of FIG.

5 is an input signal waveform diagram according to each mode in FIG.

* Explanation of symbols for main parts of the drawings

R ₁ to R ₃ : Breather resistance Pd: Input pin

CP ₁ : Channel selector CP ₁ : First tape selector

CP ₂ : first tape selector CP ₃ : second tape selector

S: analog switch G: gate circuit

The present invention relates to a circuit provided in a system circuit block of an image recording apparatus and a tape selection circuit for automatically selecting and controlling a rust processing time. Especially, a circuit input is advantageously integrated by reducing the number of input pins by tying related circuit inputs together. A signal processing control circuit of an image recording apparatus intended to simplify the configuration.

In video and audio recording apparatus using VHS system such as VTR, it has two heads and first and second channels related to tape track, and one screen field is usually formed by two channels.

Therefore, a channel select switch circuit for signal control processing associated with the VTR head is provided for the divided channels, and this channel select switch circuit is shown in FIG.

In this case, the transistors Q ₂₁ and Q ₂₂ are configured to selectively activate two channel outputs CH and CH ₂ for one input pin Pa.

In the video and audio recording apparatus as described above, there are standard SP (Standard Play,) LP (Long Play) and EP (Extend Play) modes according to the type of tape according to the recording and playback time. A tape selection circuit for processing is provided.

That is, this example is shown in FIG.

In this case, when the voltage level input according to the tape mode is applied to one input pin (Ph), the transistor (Q _{23 to} Q ₃₂ ) circuit selectively outputs the SP, LP, and EP mode outputs according to the full dark level input. Consists of.

However, these channel selection switch circuits and the tape selection circuits in FIGS. 1 and 2 are designed as separate input pins (Pa, Ph), respectively, and mounted in predetermined system circuits, which is disadvantageous when such circuits are integrated. There is a problem that it is difficult to simplify the circuit.

The present invention improves the problems of the prior art as described above, and it is particularly designed to integrate the circuit selection switch circuit and the tape selection circuit having the independent input pin structure with one input pin. It is intended to provide a signal processing control circuit for facilitating and simplifying the circuit.

Hereinafter, the present invention will be described in detail by the drawings of the embodiments.

3 also shows a circuit block of the signal processing control circuit according to the present invention.

Here, assuming that the input connection point of the channel selector switch circuit generated in the system circuit is Cb and the input connection point of the tape selector circuit is Ca, the breeder resistors R ₁ to R ₃ are respectively connected to Ca and Cb. One input pin (Pd) connected to the connection point of the breather resistors (R ₁ to R ₃ ) and the input pin (Pd) to compare the channel selection input with the reference value channel selection output (CH ₁ , CH ₂ ) The channel selector CP ₁ and the output of the channel selector CP ₁ that generate a common pin analog switch (S ₁ ) and the output of the analog switch (S ₁ ) to the input pin (Pd) The first and second tape selectors CP ₂ and CP ₃ and the gate circuit G generate the SP, LP and EP mode logic signals.

The signal processing control circuit shown in FIG. 3 shows a specific embodiment as shown in FIG.

In this case, the channel selector CP ₁ is a transistor Q ₃ , Q ₄ connected to an output terminal of a differential amplification circuit by transistors Q ₁ and Q ₂ to generate a switching logic output. The two-tap selector circuits CP ₂ and CP ₃ also have a differential amplifier circuit by transistors Q _{5 to} Q ₈ and a transistor connected to each of the output stages of the differential amplifier circuit to output three output mode signals ( Q _{9 to} Q ₁₄ ) to form a wave and gate circuit.

The present invention of such a configuration is as follows.

That is, in the system circuit, the channel select switch input and the tape select input according to the mode are applied to one pin Pd via the breather resistors R ₁ to R ₃ .

At this time, if the input condition of the pin (Pd) side is determined as shown in Table 1 below, the channel mode output and the tape mode output according to this can be obtained.

TABLE 1

The channel selection signal input to the connection point Ca becomes CH1 (Vcc) and CH2 (ground potential), and if the connection point Cb is maintained at Vcc in LP mode, open in EP mode, and ground potential in SP, You can get the input condition as table 1.

In addition, the input waveforms in the SP, LP, and EP modes according to the input mode according to the relationship shown in Table 1 are shown in FIG.

Therefore, when the tape mode is SP and the channel selection mode is CH1, the input pin (Pd) Voltage is generated, and at this time, CH2 becomes the ground potential.

When the tape mode is LP and the channel selection mode is CH1 Is generated, and CH2 is Is generated.

When the tape mode is EP and the channel selection mode is CH1 CH2 maintains the ground potential.

In addition, when the resistance values of the breather resistors R ₁ and R ₃ are assumed to be R ₁ and R ₂ , they may have an input condition according to the tape mode as shown in FIG. 5.

According to such input conditions, in the signal processing control circuit of the present invention, the differential amplification transistors Q ₁ and Q _{2 of} the channel selector CP ₁ have their input voltages equal to 1/3 Vcc (Vref _{1 in} FIG. 5). When the input level is larger than 1 / 3Vcc, the transistor Q ₁ is turned on and the transistor Q ₂ is turned off.

When the transistor Q ₂ is turned off, the transistor Q ₃ is turned on and the transistor Q ₄ is turned off so that the collector output of the transistor Q ₄ maintains logic 1 to generate the CH1 output.

In addition, the Pd-side if the input level is less than 1 / 3Vcc, the transistor (Q ₁₎ is off, the transistor (Q ₂₎ is turned on the transistor (Q ₃₎ an off-transistor (Q ₄₎ are turned on transistor (Q ₃₎ CH2 output is generated by the collector output.

In the mode in which the CH1 output is generated, input voltages corresponding to the SP, LP, and EP modes of the first, second tape selection unit CP ₂ (CP ₃ ) and the gate circuit unit G are generated through the analog switch S. When the capacitor C ₁ on the side is charged, the output for each mode is generated with this charged voltage.

As an example, resistance If it is assumed that the Pd input is ½Vcc at SP, ⅔Vcc at LP, and ¾Vcc at EP, the transistors (Q ₈ , Q ₉ , Q ₅ ) are turned on and the current mirror is turned on. A predetermined current flows through the transistor Q ₁₀ to maintain the transistor Q ₁₂ at a logic zero.

In addition, since the transistors Q ₁₃ and Q ₁₄ serve as the gates for the outputs V ₄ and V ₅ , only V ₅ maintains the output at this time _.

In the LP mode, since the transistors Q ₆ and Q ₇ are turned on, the output V ₅ of the transistor Q ₁₁ is logic 0, and as the transistor Q ₁₀ is turned off, the transistor Q ₁₀ is also turned off. maintained generates a logic one output only V _4.

In the EP, the transistors Q ₆ , Q ₅ , and Q ₉ are turned on, and the transistor Q ₁₁ is turned on. As the transistor Q ₁₀ is turned off, the transistor Q ₁₂ also remains off. Therefore, logic 1 output occurs only in V ₄ .

In the EP, the transistors Q ₆ , Q ₅ , and Q ₉ are turned on, and the transistor Q ₁₁ is turned on. As the transistor Q ₁₀ is turned on, the transistor Q ₁₂ is kept in the ON state. ₄ is logic 0, and the transistors Q ₁₃ and Q ₁₄ maintain V ₃ only in the output state by the NOR gate operation.

As described above, the present invention comprises the individual input pins of the channel selection switching circuit and the tape selection circuit of the video recording apparatus such as a VTR as a single input pin so that these circuits can be bundled together to facilitate the integration of the circuits. There is also a beneficial feature that can simplify the circuit.

Claims (1)

With one input pin (Ca) and one channel (CH ₁ ), channel 2 (CH ₂ ) signal generation terminal and one input pin (Cb) constituting one screen field, SP, LP, An image recording processing apparatus having a tape selection terminal for generating a predetermined mode output in response to a tape mode input of an EP, comprising: a resistor (R _1- R ₃ ) connected to the input pins (Ca, Cb) and the brother One input pin Pd connected to the connection point of the resistors R ₁ -R ₃ , a channel selector CP ₁ connected to the input pin Pd to generate a channel select output, and the input pin ( Comparison between the analog switch S and the output of the analog switch S controlled by the (CH ₁ ) output of the channel selector CP ₂ between the mode output and the mode output according to the voltage level for each mode. A first tape selector CP ₂ and a second tape selector CP ₃ for generating an output; the first and second tape selector And a gate circuit (G) for generating active logic signals in three modes in accordance with the output state of (CP ₂ , CP ₃ ).