KR930004106Y1 - Power circuit - Google Patents

Power circuit Download PDF

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Publication number
KR930004106Y1
KR930004106Y1 KR2019910002473U KR910002473U KR930004106Y1 KR 930004106 Y1 KR930004106 Y1 KR 930004106Y1 KR 2019910002473 U KR2019910002473 U KR 2019910002473U KR 910002473 U KR910002473 U KR 910002473U KR 930004106 Y1 KR930004106 Y1 KR 930004106Y1
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KR
South Korea
Prior art keywords
resistor
capacitor
thyristor
grounded
resistance
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KR2019910002473U
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Korean (ko)
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KR920017285U (en
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김인석
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삼화기연 주식회사
김인석
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Priority to KR2019910002473U priority Critical patent/KR930004106Y1/en
Publication of KR920017285U publication Critical patent/KR920017285U/en
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Publication of KR930004106Y1 publication Critical patent/KR930004106Y1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

내용 없음.No content.

Description

지연회로 장치Delay circuit device

첨부 도면은 본 고안을 설명키 위한 회로도.The accompanying drawings are circuit diagrams for illustrating the subject innovation.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

T1,T2: 단자 D1-D4,D6: 다이오드T 1 , T 2 : Terminals D 1 -D 4 , D 6 : Diodes

D5,D7: 제너다이오드 Q1,Q3: 사이리스터D 5 , D 7 : Zener diode Q 1 , Q 3 : Thyristor

Q2: NPN형 트랜지스터 C1-C3: 콘덴서Q 2 : NPN transistor C 1 -C 3 : Capacitor

R1-R9: 저항 VR1: 가변저항R 1 -R 9 : resistance VR 1 : variable resistor

본 고안은 지연 회로장치에 관한 것이다.The present invention relates to a delay circuit device.

종래 부하측에 전원이나 신호를 입력하는 경우 디스토숀의 발생으로 부하측기기를 손상시키는 일이 있어 이를 방지하는 회로가 많이 공개되고 있다. 그러나 이와같은 종래의 지연회로에 있어서는 기계적인 방법으로 되는것이 대부분이며, 또 전기회로에 의한 지연회로에 있어서는 회로가 복잡하여 경제적인 부담이 있었다.Conventionally, when a power supply or a signal is input to a load side, a circuit which prevents this by damaging the load side equipment by the generation of distortion has been disclosed. However, in such a conventional delay circuit, the mechanical method is mostly used, and in the delay circuit by the electric circuit, the circuit is complicated and there is an economic burden.

본 고안은 상기와 같은 점을 감안하여 안출된 것으로 회로가 간단하기 때문에 경제적이며 또 동작이 확실하도록 된 것으로 이하 본 고안을 첨부된 도면에 따라 설명하면 다음과 같다.The present invention has been devised in view of the above-mentioned point, and since the circuit is simple, economical and reliable operation will be described below with reference to the accompanying drawings.

첨부도면은 본 고안을 설명키 위한 회로도로 단자(T1)와 (T2)사이에는 다이오드(D1-D4)에 의해 브리지 정류회로가 구성되어 출력측의 마이너스는 접지되며 출력측의 플러스에는 저항(R1)과 콘덴서(C1)가 접지 사이에 직열로 연결하여 써지 전류를 흡수토록 되고 또한 스위칭 소자인 사이리스터(Q1)의 애노드와 캐소드가 상기 한 브리지 정류회로의 플러스측에 연결되며 또 사이리스터(Q1)의 게이트는 회로 공급 전압유지용 제너다이오드(D5)와 저항(R2)이 직열로 하여 브리지 회로의 플러스에 연결되어 있다.The accompanying drawings are circuit diagrams for explaining the present invention. A bridge rectifier circuit is formed by diodes D 1 -D 4 between terminals T 1 and T 2 so that the negative side of the output side is grounded and the positive side of the output side has a resistance. (R 1 ) and capacitor (C 1 ) are connected in series between ground to absorb surge current, and the anode and cathode of thyristor (Q 1 ), which is a switching element, are connected to the plus side of the bridge rectifier circuit. The gate of the thyristor Q 1 is connected to the positive of the bridge circuit with the zener diode D 5 for holding the circuit supply voltage and the resistor R 2 in series.

또 상기한 플러스 출력은 저항(R3)을 통해 일측이 접지된 제너다이오드(D7)와 콘덴서(C4)에 연결되어 제너다이오드(D7)에 의해 정전압은 콘덴서(C4)로 평활하여 아래 설명하는 회로의 전원을 공급 하도록 되어 있다.In addition, the positive output is connected to a zener diode (D 7 ) and a capacitor (C 4 ) grounded at one side through a resistor (R 3 ) so that the constant voltage is smoothed to the capacitor (C 4 ) by the zener diode (D 7 ). It is intended to supply power to the circuit described below.

즉 상기한 평활화되고 정전압으로 된 전원이 저항(R9)과 가변저항(VR1)을 통해 콘덴서(C3)를 충전하도록 되며 저항(R5)과 저항(R6)으로 분지된 전압이 타임 디레이소자인 사이리스터(Q3)의 게이트에 공급됨과 동시애노드가 저항(R8)으로 접지된 사이리스터(Q3)의 캐소드에는 상기한 콘덴서(C3)와 에미터 접지된 NPN형 트랜지스터(Q2)의 콜렉터에 직열 연결된 저항(R4)과 다이오드(D6)로 되는 휘드백소자가 연결되며, 또한 상기한 NPN형 트랜지스터(Q2)의 콜렉터는 상기한 제너다이오드(D5)와 일측이 접지된 콘덴서(C2)에 연결하여서 된 것이다.That is, the smoothed and constant voltage power source is charged to the capacitor C 3 through the resistor R 9 and the variable resistor VR 1 , and the voltage divided by the resistor R 5 and the resistor R 6 is timed. the delay element is a thyristor (Q 3) are simultaneously anode as soon fed to the gate resistor (R 8) a cathode of grounded thyristor (Q 3), the above-mentioned capacitor (C 3) and an emitter grounded NPN transistor (Q with the 2 ) a resistor R 4 connected in series with the collector of the resistor and a feedback device including a diode D 6 are connected, and the collector of the NPN transistor Q 2 is connected to the zener diode D 5 on one side. This is connected to the grounded capacitor (C 2 ).

도면중 미설명부호(R7)은 NPN형 트랜지스터(Q2)의 베이스 저항을 의미한다.In the figure, reference numeral R 7 denotes the base resistance of the NPN transistor Q 2 .

상기와 같은 구성으로 되는 것이므로 도시하지 않은 부하측과 전원 사이에 직열로 상기 단자(T1)와 (T2)를 연결하여 전원을 ON하는 경우 저항(R9)과 가변저항(VR1)에 의해 콘덴서(C3)과 충전되었다가 전압이 높아진느 경우 타임디레이 소자인 사이리스터(Q3)의 게이트와 캐소드는 양측에 걸리는 전압을 비교하는 비교기 역할을 하게 되고 콘덴서(C3)의 양단 전압이 높아짐에 따라 비교기인 사이리스터(Q3)의 애노드-캐소드 사이가 도통됨으로 저항(R6)으로 타임디레이 신호를 사이리스터(Q1) 게이트 신호용 NPN형 트랜지스터(Q2)의 베이스를 트리거하던 전압이 강하되어 트랜지스터는 ON되고, 이에 따라 제너다이오드(D5)는 콘덴서(C2)의 충전이 완료되는데 따라 도통 전압을 받아 스위칭 소자인 사이리스터(Q1)를 도통시켜 다이오드(D1-D4)로 되는 브리지회로가 ON됨으로서 도시하지 않은 부하측에 정상전류를 ON하게 되는 것이다.Since it is configured as described above when the power is turned on by connecting the terminals (T 1 ) and (T 2 ) in series between the load side and the power source (not shown ) by the resistor (R 9 ) and the variable resistor (VR 1 ) When charged with the capacitor (C 3 ) and the voltage increases, the gate and cathode of the thyristor (Q 3 ), the time delay element, serve as a comparator to compare the voltage across both sides, and the voltage across the capacitor (C 3 ) As the voltage increases, the anode-cathode of the comparator thyristor (Q 3 ) becomes conductive, so that the voltage that triggers the time delay signal with the resistor (R 6 ) to the base of the NPN transistor (Q 2 ) for the thyristor (Q 1 ) gate signal the drop transistor is oN, thus a Zener diode (D 5) is a capacitor receiving the conduction voltage charging is completed, there is according to the (C 2) diode to conduct the thyristor switching element (Q 1) (D 1 -D 4) Being By turning on the bridge circuit, the normal current is turned on at the load side (not shown).

상기와 같이 본 고안에 의하면 가변저항(VR1)과 콘덴서(C3)의 시정수에 의해 부하측에 지연된 전원이 인가되도록 하는 것이므로 고장의 염려가 없고 구성이 간단하면서도 작용이 확실하여 실용성 있는 고안인 것이다.As described above, according to the present invention, since the delayed power is applied to the load side by the time constants of the variable resistor VR 1 and the capacitor C 3 , there is no fear of failure and the configuration is simple but the operation is sure and practical. will be.

Claims (1)

전원단자 사이에 저항(R1)과 콘덴서(C1)가 직열로 연결되고 사이리스터(Q1)의 애노드-캐소드가 연결되고 상기 사이리스터(Q1)의 게이트에 제너다이오드(D3)와 저항(R2)으로 전원에 연결됨과 동싱 에미터 접지된 NPN 트랜지스터(Q2)의 콜렉터가 연결되며 상기 콜렉터에는 콘덴서(C2)로 접지됨과 동시 저항(R4)과 다이오드(D6)로 되는 피드백 소자가 콘덴서(C3)를 통해 접지되고, 상기 콘덴서에는 저항(R9)과 가변저항(VR1)을 통해 연결되고 저항(R8)으로 애노드 접지된 온 쇼트 타임디레이 소자인 사이리스터의 캐소드에 연결되며, 게이트는 저항(R5)과 저항(R6)의 분기 전압이 연결하여서 되는 지연회로장치.Resistance between the power supply terminal (R 1) and a capacitor (C 1) the anode of the connection to the direct thermal and thyristor (Q 1) - gate zener diode (D 3) on the cathode is connected and the thyristor (Q 1) and a resistance ( R 2 ) is connected to the power supply and the collector of the same emitter grounded NPN transistor (Q 2 ) is connected, which is grounded by a capacitor (C 2 ) and fed back with simultaneous resistance (R 4 ) and diode (D 6 ). The cathode of the thyristor, an on-short time delay element, whose device is grounded through a capacitor C 3 , which is connected via a resistor R 9 and a variable resistor VR 1 and an anode grounded by a resistor R 8 . The delay circuit device is connected to, the gate is connected to the resistor (R 5 ) and the branch voltage of the resistor (R 6 ).
KR2019910002473U 1991-02-22 1991-02-22 Power circuit KR930004106Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910002473U KR930004106Y1 (en) 1991-02-22 1991-02-22 Power circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910002473U KR930004106Y1 (en) 1991-02-22 1991-02-22 Power circuit

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KR920017285U KR920017285U (en) 1992-09-17
KR930004106Y1 true KR930004106Y1 (en) 1993-06-30

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KR920017285U (en) 1992-09-17

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