KR930003721B1 - Data system with high interrupt punction - Google Patents

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Description

Data processing system with high speed interrupt function

1 is a block diagram of a system including an apparatus of the present invention.

2 is a block diagram of the interface logic of a processing unit including the apparatus of the present invention.

3 is a detailed diagram of the interrupt logic of the present invention.

4 is a format diagram of instructions utilized in the apparatus of the present invention.

* Explanation of symbols for main parts of the drawings

2: System bus 4,4A: Central subsystem (CSS)

8,8A: Main memory 12,14: Peripheral controller

16,18 Peripheral device 20 System management device (SMF)

The present invention relates to data systems, in particular interrupt devices used in connection with such systems.

As is well known, most data processing systems employ interrupt devices in their processing units to provide priority services for interrupt requests from competing devices. Such service functionality is typically accomplished by assigning interrupt priority levels to competing devices, comparing the levels, and allowing a higher priority device to access the system or processing unit, which device After the request of is serviced, a signal is sent from the processing unit to other devices indicating that service for new interrupts can be made at the current interrupt level. Systems of this type have been disclosed, for example, in US Pat. No. 3,984,820.

On the other hand, US Patent No. 4,371,928 discloses a data processing system in which an interrupt instruction includes a source priority level. In this type of system, however, there is a problem that if a command other than the current command is received from the asynchronous system bus, the current command cannot be quickly responded.

On the other hand, US Patent No. 3,993, 981 discloses a system employing a comparator means for comparing the interrupt level of a command currently being executed with the interrupt level of a new command received via the system bus.

However, today's more complex multiprocessing systems must be able to respond quickly to commands that indicate over-tolerance conditions or feature time-lapse states so that sequential shutdown of the system is possible. In addition, for certain time-lapse states, while software processing is being executed, a faster real-time change is required than was previously possible. This is particularly necessary when many peripheral controllers are each requesting access to the CPU at about the same time.

It is therefore a primary object of the present invention to provide an improved interrupt apparatus for use in a multiprocessing system.

Another object of the present invention is to provide an interrupt device that operates at a normal speed and a high speed.

The above objects and advantages of the present invention are achieved through the preferred embodiments of the multi-processing system shown in the accompanying drawings and described in detail below. The apparatus of the present invention is included in the interrupt logic of the bus interface circuit of each processing unit of the system, through which the interrupt logic communicates with the remaining units of the system, via the interface circuits, to respond to normal and fast interrupt requests. Commonly coupled to an asynchronous system bus.

During normal operation, instructions including address signals, data signals and control signals are transmitted over the system bus. Each processing unit receives each of the above commands and specific control and address signals to determine whether to execute the command. A processing unit that recognizes that the decoded address signals are its unique channel number compares the interrupt priority level of the instruction currently being executed by the processing unit with the interrupt priority level of the new instruction. If the new instruction has a higher priority level than the currently executing instruction, the processing unit sends an acknowledge signal via the system bus to the source unit, i.e., the unit from which the new instruction originated. On the other hand, if the new command has a Zhou priority level than the running command, the processing unit sends a not acknowldege signal on the system bus. In this case, the source unit sends a command back to the processing unit after a predetermined time delay.

By the way, certain commands, in particular overheating, specified power over, or specific time elapsed conditions, require an immediate response to the processing unit. These instructions will have special control and address signals indicating that immediate instruction execution is required, whereby the processing unit addressed with these instructions will immediately interrupt the currently executing instruction and execute the new instruction.

Specific control and address signals are applied to the array logic. Among these, the control signals indicate that this command is not a response to the previous command, that it is not a level change command, and that the address signals contain a channel number, and that the command is a normal interrupt command. Or a high speed interrupt command.

Output signals from the array logic enable level comparison logic, allowing the enable or disable signal for a command requiring a normal interrupt to be sent out on the system bus. For high speed operation, other outputs from the array logic bypass the level comparison logic, causing a grant or disable signal to be initiated.

Two processing units can be included in a single central subsystem coupled to an asynchronous system bus by a single interface, in which case the array logic decodes the address signals representing the channel numbers, so that any processing unit While indicating that it is responding, the level comparison bypass logic is started for a fast response, or the level comparison logic is used for a normal response.

The manner in which the method of the present invention is performed, the manner in which the apparatus of the present invention is configured, the mode of operation thereof, and the like will be clearly understood from the following detailed description with reference to the accompanying drawings.

1 is a block diagram of a multiprocessing system 1 having a number of subsystems, each coupled to an asynchronous system bus 2 via a separate interface.

In FIG. 1, one central subsystem (CSS) 4 is coupled to the system bus 2 via interfaces MRI0 (2-10), MRIC (2-30), and another central subsystem. (CSS) 4A is coupled to the system bus 2 via interfaces MRI2 (2-10A) and MRIC (2-30A) and MRI3 (2-20A). Interface MRI0 (2-10) is identified as port 0 and interface MRI1 (2-20) is identified as port 1. Interface MRICs 2-30 provide registers in common for both port 0 and port 1. Although only two CSS are shown in the figure, it will be appreciated that any number of CSS may be coupled to the system bus 2 via their respective interfaces. Each interface region includes a bus interface logic circuit of the type as disclosed in FIG. 9 of US Pat. No. 3,995,258.

The system bus 2 is further connected with a system management apparatus (SMF) 20 via an interface MBI 2-8. Also, a plurality of main memories, i.e., main memories 8 to 8A, are coupled to the system bus 2 via their respective interfaces MBI 2-12 to MBI 2-12A. Also, a number of peripheral controllers, i.e., peripheral controllers 12 to peripheral controllers 14, are coupled to the system bus 2 via their respective interfaces MBI 2-22 to MBI 2-24. A plurality of peripheral devices 16 are connected to the peripheral controller 12, and a plurality of peripheral devices 18 are also connected to the peripheral controller 14 as well. Peripherals 16-18 include, but are not limited to, keyboards, displays, communication devices, disk drivers, tape drivers, printers, and document readers.

Each CSS has two central processing units (CPUs) each having a virtual memory management unit (VMMU), and one cache. That is, the CSS 4 includes a CPU0 / VMMU 4-2, a CPU1 / VMMU 4-4, and a cache 4-6. CPU0 / VMMU (4-2) is coupled to the system bus (2) via interfaces MRI0 (2-10) and MRIC (2-30) and port 0, and CPU1 / VMMU (4-4) is connected to interface MRI1 ( 2-20) and the MRIC (2-30) and port 1 to the system bus (2). Both CPUs, namely CPU0 / VMMU 4-2 and CPU1 / VMMU 4-4, are also associated with port 0 and port 1 of cache 4-6, respectively. The cache 4-6 is coupled to the system bus 2 via the interface MRI0 (2-10) and port 0 when it interacts with the CPU0 / VMMU 4-2, and it is connected to the CPU1 / VMMU 4-4. ) Is coupled to the system bus (2) via interfaces MRI1 (2-20) and port 1. In addition, the CSS 4 receives information from the system bus 2 through the interface MRIC 2-30.

The units of CSS 4A, i.e., CPU2 / VMMU (4-2A), CPU3 / VMMU (4-4A), and cache (4-6A), also operate in the same way, using interfaces MRI2 (2-10A), MRIC (2- 30A) and MRI3 (2-20A) to the system bus (2).

SMF 20 not only controls the initialization of system 1, but also monitors many system and environmental functions. The SMF 20 includes a watch dog timer and a real time clock, which are set by instructions received via the system bus 2 from one of the CPUs. When the watchdog timer or real time clock has decreased to zero, the SMF 20 responds by sending a corresponding command to the CPU that originally set the clock via the system bus 2. Moreover, the SMF 20 monitors power and temperature and issues instructions via the system bus 2 to warn the CPUs to take proper action. If the power or temperature falls below a preset value, the CPUs allow the operating system software to enable sequential retries (resume) immediately after receiving a power warning or temperature warning command to shut down the system sequentially. Answer by preparing for More specific operation of the SMF 20 is described in detail in US Patent Application No. 869,164 (name of the invention: "System Management System of a Multiprocessor System") related to the present application.

The system 1 of FIG. 1 is configured as a multi-CPU system that is tightly coupled because each CPU executes a single operating system and shares a common main memory. Therefore, each CPU interrupts another CPU or itself by interprocess instructions, i.e., interprocessor instructions. All communication between subsystems takes place over the system bus 2 via commands and responses to those commands.

The SMF 20 is arranged to give highest priority access to the system bus 2. Since many instructions are generated by the SMF 20 that require fast access to the CPU, this preferred position ensures that the addressed CPU responds quickly to the instructions.

The CPU will execute the instructions of a given process at a defined interrupt level. Only when a command is received from the system bus 2 to call the CPU to execute a higher priority process, the CPU will interrupt the running process.

When the CPU receives an instruction initiated by another subsystem, the CPU checks the interrupt priority level of the instruction, and if the instruction has a higher priority than the instruction being executed, the system bus 2 as an enable signal. Respond via On the other hand, if the interrupt instruction has a higher priority than the instruction being executed, the CPU will respond with a no signal. The subsystem that issued the command receives a grant or non-response response to cause the appropriate action. When a non-response is received, the start subsystem sends a command back to the CPU via a system bus. At this time, if the CPU executes a Zhou priority instruction, the CPU receives the instruction and sends a permission signal through the system bus 2.

However, certain instructions require the CPU receiving the instructions to cause an immediate action. In this case, the CPU will respond to the specific instructions through the logic of the present invention to immediately interrupt the currently running process and execute the process called by the new instruction, as described in this embodiment. Representative commands that require an immediate response are SMF 20 commands that relate to a time-lapse state, a power or temperature change state, and a status change state. In addition, certain CPU-to-CPU instructions also require an immediate response. In this case, one CPU interrupts another through logic that responds to certain signals in the instruction.

2 is a block diagram of interfaces MRI0 (2-10), MRI1 (2-20) and MRICs (2-30). Port 0 interface MRI0 (2-10) logic is identified by elements of (2-1XX). Port 1 interface MRI1 (2-20) logic is identified by elements of (2-2XX). The common interface MRIC 2-30 logic for receiving information from the system bus 2 is identified by elements of (2-3XX).

The system bus 2 comprises a system data bus 2-4, a system address bus 2-6 and a system control bus 2-2. The data bus 2-4 includes 32 data signals BSDT00-BSDT31-and a plurality of parity signals (not shown). Here, a minus sign (-) indicates a binary '1' when the signal is 'low' and a binary '0' when the signal is 'high'. The address bus 2-6 includes 32 address signals BSAD00-BSAD31-and a plurality of parity signals (not shown). The control bus 2-2 includes a plurality of control signals. Hereinafter, only control signals related to the present invention will be described.

Any subsystem can request and gain access to the system bus 2 in order to pass information to another system. The information is in the form of a command or a response to a command. It is also possible for any CPU to request access to the system bus 2 in order to transfer information to itself, another CPU, or another subsystem, and obtain that access. Each interface receives the information and determines whether the information includes the address or channel number of a unit coupled to that interface. If the information received by the interface does not include the channel number of the unit or subsystem coupled to that interface, the information is ignored. When the memory reference signal BSMREF + indicates that the channel numbers indicating the main memory storage location are not included in the address signals BSAD00 + to BSAD31 +, the bus address signals BSAD08-17 + are decoded to form the channel number. On the other hand, when the information is addressed to the subsystem, the subsystem notifies that the information has been received by sending the permission signal BSACKR- on the system bus 2.

That is, the subsystem accepts the information if its information is provided with its channel number and the subsystem is not executing a process with higher order. If the subsystem is unable to accept the information because it is executing a higher priority process, it will send an irrelevant signal BSNAKR- on the system bus 2.

Referring to FIG. 2, interface MRICs 2-30 include two sets of command receiving registers configured to operate in first-in first-out (FIFO) mode. Assuming that the first command received by interface MRIC 2-30 is stored in the first set of registers and that it is recognized, the next command will be received by the second set of receive registers. On the other hand, the CPU that failed to respond to its channel number receives the instruction by not loading the instruction from the first set of receive registers when the instruction stored in the second set of receive registers is recognized. Make the registers valid for the next instruction. If a command stored in the second set of receive registers is not recognized, the command is ignored and the next command is stored in the second set of registers.

The data signals BSDT00-31- from the data bus 2-4 are each received by 32 inverting receivers 2-302. Assume that these data signals are stored in the first set of receive registers. These data signals are inverted into signals BSDT00-31 + and stored in eight registers AREGA 2-308. Here, the plus sign indicates that the logic '1' signal is 'high' and the logic '0' signal is 'low'. Similarly, address signals BSAD00-31- from address bus 2-6 are each received by 32 inverting receivers 2-304, inverted into signals BSAD00-31 +, and then eight registers AREGA (2). And a plurality of control signals are each received by the same number of inverting receivers 2-306 and then stored in the register CREGA 2-312.

Interrupt logic 2-50 compares the channel number appearing as signals BSAD08 + to BSAD18 + with a preset channel number and determines whether the interrupt level of the just received instruction has a higher priority than the instruction being executed. As a result, if the channel number signals indicate the CPU 4-2, the CPU 4 through the registers IDREGA (2-112) and IDREGA (2-110) and the internal data bus D0 (2-108). 2) an authorization response is given, and data and address information is transferred. If the channel number signals indicate the CPU 4-4, data and address information is passed through the registers IDREGB (2-212) and IDREGB (2-210) and the internal data bus D1 (2-208). 4-4).

If the information does not include the channel number of the CPU 4-2 or CPU 4-4, the instructions stored in the registers DREGA (2-308), AREGA (2-310) and CREGA (2-312). No action takes place for. Then, the next command received via the system bus 2 is stored in the same registers as above.

When multiple instructions are sent to the CPU 4-2 or 4-4 in succession, the information of the first recognized instruction is stored in registers 2-308, 2-310 and 2-312. The information of the second recognized instruction is stored in the registers DREGB (2-314), AREGB (2-316) and CREGB (2-318). If a third command is received, the contents of registers 2-308, 2-310, and 2-312 will be delivered to the addressed CPU, and thus the registers 2-308, 2 And 310-212 receive the third command.

Registers 2-308, 2-310 and 2-312 are enabled by the write enable signal WRTSLA-. Registers 2-314, 2-316 and 2-318 are enabled by the write enable signal WRTSLB-. The signals WRTSLA- and WRTSLB- are complementary signals and toggle during each SystemBus 2 cycle in which the received command is recognized. The read enable signal REDENA- validates the output signals of registers 2-308, 2-310 and 2-312, and the read enable signal REDENB- registers 2-314, ( 2-316) and (2-318) output signals are valid. The signals REDENA- and REDENB- are also complementary signals and toggle with a phase difference from the write enable signals WRTSLA- and WRTSLB-.

Control signals BSMREF +, BSUELO +, BSSHBC +, BSWRIT + and BSRINT + are received by interrupt logic 2-50.

The signal BSSHBC + indicates that this command provides information in response to a command from the subsystem that requested the information.

The signal BSRINT +, issued by the CPU, indicates that the CPU, has changed the interrupt priority level, and that the I / O devices can make an attempt to resume interrupting. The I / O device, which had previously made an attempt to interrupt the CPU and received an impossible signal, will not issue any more interrupts until it detects that the signal BSRINT- is true on the system bus 2.

The signal BSMREF + of logic '0' indicates that the address signals BSAD08-17 contain the channel number.

Signal BSYELO + of logic '1' and signal BSMREF + of logic '0' indicate that this is the highest priority command and initiates a high speed interrupt operation.

CPU0 (4-2) or CPU1 (4-4) generate instructions to be transferred to another subsystem, another CPU, or itself via the system bus (2).

Some instruction information is stored in the cache or otherwise stored in the main memories 8 to 8A. If the information is not stored in the cache, the CPU issues an instruction to the main memories 8 to 8A and requests data in the storage specified by the address signals BSAD00-31 in that instruction. do. For this command signal, BSMREF + will be 'high'.

CPU 4-2 sends address signals to port 0 of cache 4-6 via internal address bus A0 (2-114), and CPU 4-4 sends internal address bus A1 (2-214). Sends address signals to port 1 of cache 4-6. Further, the CPU 4-2 receives data signals from the port 0 of the cache 4-6 via the data bus D0 2-108, and the CPU 4-4 receives the data bus D1 2-208. Receive data signals from port 1 of cache 4-6.

Data signals from port 4 of CPU 4-2, i.e. cache 4-6, are stored in register DREG0 (2-102) as signals P0DT00-31 + received via data bus D0 (2-108). , Data signals from port 4 of CPU 4-4, i.e. cache 4-6, are stored in register DREG1 (2-202) as signals P1DT00-31 + received via data bus D1 (2-208). do. These data signals are wired-OR to signals MYDT00-31 + and then passed to 32 inverting drivers DRVD (2-26), which are converted to signals BSAD00-31- and converted to data bus (2-4). Delivered to the prize.

Similarly, address signals from the CPU 4-2 are stored in the register AREG0 (2-104) as signals P0D00-31 + received via the address bus A0 (2-114) and sent to the CPU 4-4. Address signals are stored in register AREG1 (2-204) as signals P1AD00-31 + received via address bus A1 (2-214). These two sets of signals are wired ORed to signals MYAD00-31 + and then transferred to the address bus 2-6 as signals BSAD00-31- via 32 inverting drivers DRVA 2-28.

Control signals from the CPU 4-2 are transmitted to the control bus 2-2 via the CPU0 control storage device 4-200, the register CREG0 (2-106), and the inverting driver DRVC 2-30. The control signals from the CPU 4-4 are applied to the control bus 2-2 via the CPU1 control storage device 4-400, the register CREG1 2-206, and the inverting driver 2-30. . Logic circuits (not shown) for transferring data, address and control signals between the system bus 2 and the registers are conventional in their design, for example in the form disclosed in US Pat. No. 3,995,258. You can use

The registers shown in FIG. 2 are also common and consist, for example, of 74 AS 823 logic elements manufactured and sold by Texas Instruments.

Referring to FIG. 3, the detailed logic configuration of interrupt logic 2-50 is shown. The channel number of the receiving subsystem or CPU is identified by the address signals BSAD08 + to BSAD17 +. The channel number of the CPU 4-2 is arbitrarily assigned to hexadecimal 0000, and the channel number of the CPU 4-4 is assigned to hexadecimal 0040.

For the channel numbers of the CPU 4-2, the signals BSAD08 + to BSAD17 + are all binary '0', and for the channel numbers of the CPU1 4-4, the signals BSAD08 + to BSAD16 + are all binary '0' and signal BSAD17 + is binary '1'. Note that the hexadecimal notation begins with the signal BSAD00 +, so that the signals BSAD18 + and BSAD19 + represent the two lower bits after the lower hexadecimal, and the signals BSAD20 + to BSAD23 + represent the lower hexadecimal. For the purpose of indicating the channel number, the signals BSAD18 + and BSAD19 + are treated as being the upper two bits of the function code indicated by the signals BSAD20 + to BSAD23 +. This function code represents an operation performed by the receiving subsystem as a result of recognizing a command received via the system bus 2.

The channel number signals BSAD08 + to BSAD12 + received from the address bus 2-6 via the receiver 2-304 are applied to the negative AND gate 2-502, which are all binary '0' (low) and thus output. The signal CPCHAN + OA becomes binary '1' (high). The address signals BSAD13 + to BSAD15 + received from the address bus 2-6 via the receiver 2-304 are applied to other negative AND gates 2-504, which are also 'low', so that the output signal CPCHAN + OB also becomes 'high'. The signal BSMREF + received from the control bus 2-2 via the receiver 2-306 is 'low' when the address signals BSADO8 + to BSAD17 + represent the channel number. The bus data signal delay signal BSDCND +, when it is 'low', indicates that the system bus 2 cycle is within the first 60 nsec range of the system bus 2 cycle.

The signals CHANLO + and BSAD16 + applied to the programmable array logic (PAL) 2-506 are the channel numbers of the CPUO 4-2 or the CPU1 4-4 of the CSS 4, or the CSS ( Identifies whether the channel number is the CPU2 (4-2A) or the CPU3 (4-4A) of 4A.

Channel number signal BSAD16 + for CPU0 (4-2) and CPU1 (4-4) is 'low', and channel number signal BSAD16 + for CPU2- (4-2A) and CPU3 (4-4A) is 'high' . Therefore, for the CPU0 4-2 and the CPU1 4-4, the signals BSAD16 + and CHANLO + are both 'low', and therefore the output signal CPCHAN + OC is 'high'. The signal CHANLO + identifies the physical slot on the backplane of the system 1 to which the wiring board containing the logic of the CSS 4A is plugged.

The boolean expression for the signal CPCHAN + OC is

The signals CPCHAN + OA, CPCHAN + OB and CPCHAN + OC are all 'high' and are applied to the NAND gate 2-508. In addition, when the information received via the system buses (2-4), (2-6), and (2-2) respectively indicates correct parity, the signals BSDPOK +, BSAPOK +, and BSCPOK + are all ' High '. Therefore, the channel OK output signal CHANOK- becomes 'low', which indicates that the information on the system bus 2 will be processed by the CPU0 (4-2) or the CPU1 (4-4).

The signal CHANOK- enables the register 2-518 to return signals applied to its input terminals when the data bus signal cycle delay signal BSDCND + rises 60 nsec after the start of the system bus 2 cycle. Let time.

For fast response to the command, signal BSYELO + is high and signal BSMREF + is low. If the output signal PXSCFA + 00 from the array 2-506 is 'high', the disable signal BSNAKR + is sent out on the system bus 2 as the signal BSACKR-. The Boolean expression for the signal PXSCFA + indicating the grant response is

The signal BSSHEC +, when low, indicates that this is not a second half bus cycle received in response to a previous command issued on the system bus 2.

The signal BSRINTI, when high, indicates that the execution of this command will result in a level change and a permission response should be given. If this is not a level change command, the signal BSRINT + is 'low', indicating that the CPU1 (4-4) is not busy.

The signal BSAD17 + is "low" and the signal POSCFB + is also "low", indicating that the CPU0 (4-2) is not busy. Therefore, the permission response signal BSACKR + is sent out on the system bus 2 as the signal BSACKR-.

The Boolean expression for the signal PXSCFN + indicating no response is

This indicates that when the CPU to which its channel number is assigned is busy, that is, when the corresponding signal POSCFB + or P1SCFB + is 'high', the impossible response signal BSNAKR + is sent out on the system bus 2 as the signal BSACKR +. The output signal POSCFB + from the busy flop 2-554, when high, indicates that the CPU0 4-2 is busy. The output signal P1SCFB + from the busy flop 2-546, when high, indicates that the CPU1 4-4 is busy.

The flop 2-554 is set when the signal POSCFA + 10 from the register 2-518 rises. The signal POSCFA + is generated by the array 2-506 according to the following Boolean expression.

Signal POSCFA + is retimed by register 2-518, resulting in signal POSCFA + 10. The flop 2-554 is set when the signal POSCFA + 10 rises because the high function code signal BSAD18 + is high for the fast interrupt instruction from the SMF 20. The signal BSAD18 + may be 'low' for some instructions issued from the SMF 20 during a cyclic check operation requiring a fast interrupt, since the CPUs are assumed to be inactive during the check period. Once the flop 2-554 is set, it remains set because the output signal POSCFB- which is 'low' is applied to its set input terminal.

The flop 2-554 remains set until CPU0 4-2 completes executing the instruction. CPU0 4-2 then issues a command to itself that causes reset signal POSCFB- to be 'low'. For an instruction to the reset flop 2-554, the data signal BSDT9 + is 'high' and stored in the register 2-551 at the time of the rise of the signal POSCFA + 10. The output signal POSCFB- is forced to 'low' to reset busy flop 2-554. The register 2-556 is reset by the signal BSRINT +, which becomes 'low' at the end of the system bus 2 cycle.

CPU0 (4-2) now recognizes the command requesting the fast interrupt.

The flop 2-546 operates in the same manner as the flop 2-554, indicating that upon its set, the CPU1 4-4 is busy. The CPU1 4-4 does not recognize the instruction requesting the high-speed interrupt until the flop 2-546 is reset.

The signal P1SCFA + is generated according to the following Boolean expression.

Signal P1SCFA + from array 2-506 is retimed by register 2-518, resulting in signal P1SCFA + 10. The flop 2-546 is set upon the rise of the signal P1SCFA + because the signal BSAD18 + is 'high'. As a result, the output signal P1SCFB + becomes 'high' and is applied to the array 2-506 to prohibit the permission response to the command having the channel number of the CPU1 4-4 requesting the high speed interrupt. The signal P1SCFB0 keeps the flop 2-546 in the set state until it is reset itself by another instruction of the CPU1 4-4. A signal is generated again by this command, and the signal BSDT9 + is stored in the register 2-553. The reset signal P1SCFB- is forced to 'low' to reset the flop 2-546. Then, the signal BSRINT + goes low, and resets the registers 2-553 at the end of the system bus 2 cycle.

The permission signal for the high-speed interrupt generated by the signal PXSCFA + is applied to the OR gate 2-520, and its output signal PXACKR + is applied to the OR gate 2-522, resulting in the signal MYACKR +. This signal MYACKR + is applied to the driver 2-530, and as a result, the signal BSACKR- is generated on the system bus 2.

Similarly, the impossible signal BSNAKR- is generated by the PXSCFN +, the register (2-518), the signal PXSCFN + 10, the OR gate (2-526), the signal MYNAKR +, the driver (2-532), and the system bus (2) signal BSNAKR-. Is generated.

The signal MYACKR + is also received from the system bus 2 such that the instructions stored in the registers 2-308, 2-310 and 2-312 of FIG. 2 are held in those registers for subsequent execution. Generate the signal WRTSLB-. The next instruction is stored in registers 2-314, 2-316 and 2-312. When the command is recognized, the complementary signal WRTSLA- is generated, and the registers 2-308, 2-310 and 2-312 become valid.

Normal system bus 2 interrupt operation is initiated when the signal BSYHLO + of the received command is 'low'. In this case, if the information on the system bus 2 is for interrupting the CPU 0 (4-2), the signal POINTR- is generated from the array 2-506, while the information on the system bus 2 is sent to the CPU 1 (4-4). Signal P1INTR- is generated to interrupt

The boolean expression for these signals is:

The signal POINTR- is also applied to the input terminals of the negative AND gate (2-510) and (2-514). The signal POLVLS- is applied to the other input terminal of the negative AND gate 2-510, and the signal POLVLS + is applied to the other input terminal of the negative AND gate 2-514.

Similarly, the signal P1INTR- is applied to the input terminals of the negative AND gates 2-512 and 2-516. The signal P1LVLS- is applied to the other input terminal of the negative AND gate 2-512, and the signal P1LVLS + is applied to the other input terminal of the negative AND gate 2-516.

The signal POLVLS-, when low, indicates that the CPU0 4-2 is executing a more dominant priority routine and an authorization response is sent over the system bus 2.

The signal P1LVLS-, when low, indicates that the CPU1 4-4 is executing a lower priority routine and an authorization response is sent over the system bus 2.

Signal POLVLS + and signal P1LVLS +, when low, indicate that CPU0 (4-2) or CPU1 (4-4) are executing higher priority routines respectively and a non-response is sent via system bus (2).

Output signals POINTA +, P1INTA +, POINTN + and P1INTN + from negative AND gates 2-510, 2-512, 2-514 and 2-516 are stored in register 2-518, respectively. do.

For the permission response, if either signal P0INTA + or P1INTA + applied to OR gate 2-524 is 'high', driver 2-530, signal MYACKR +, OR gate 2-522, and signal The signal BSACKR- is generated via PXINTA +. For a no response, if either signal POINTN + or P1INTN + applied to OR gate 2-528 is 'high', driver 2-532, signal MYNAKR +, OR gate 2-526 and signal The signal BSNAKR- is generated via PXINTN +.

The priority level comparison for CPU0 4-2 is made by level comparator 2-550. Priority level comparison for CPU1 4-4 is made by level comparator 2-552. Comparator 0 (2-550) compares the priority levels of the routines being executed by CPU0 (4-2), and comparator 1 (2-552) compares the priority levels being executed by CPU1 (4-4). do. The interrupt priority level of the new command is applied to the comparators 2-550 and 2-552 as data signals BSDT00-15 +.

Both comparators 2-550 and 2-552 compare the input interrupt priority levels indicated by data signals BSDT00-15 + with the interrupt priority levels stored in each comparator. Signal P0LVLS-, when low, indicates that the interrupt priority level of the new instruction is higher than the interrupt priority level of the instruction executing on CPU0 (4-2). Signal P1LVLS-, when low, indicates that CPU1 4-4 is executing a lower interrupt priority level command. Signals POLVLS- and P1LVLS- are applied to negative AND gates 2-510 and 2-512, respectively.

The signal POLVLS +, when low, indicates that the CPU0 4-2 is executing an interrupt priority level instruction higher than the interrupt priority level of the new instruction. Signal P1LVLS +, when low, indicates that CPU1 4-4 is executing an interrupt priority level instruction that is higher than the interrupt priority level of the new instruction. Signals POLVLS + and P1LVLS + are applied to negative AND gates 2-514 and 2-516, respectively.

Signals P0INTR- from array 2-506 are applied to negative AND gates 2-510 and 2-514 and 'low', indicating a permission response from negative AND gate 2-510. Signal P0LVLS- is selected to generate P0INTA +, or signal P0LVLS + is selected so that a signal P0INTN + indicating an unresponsive response is generated from negative AND gate 2-514.

Signal P1INTR- from array 2-506 is applied to negative AND gates 2-512 and 2-516, and if 'low', generates signal P1LVLS- to generate signal P1INTA + for a grant response. Select signal P1LVLS + to generate a signal P1INTN + for non-response.

Signals P0INTA +, P1INTA +, P0INTN + and P1INTN + are stored in register 2-518. The output signals P0INTA + 10 and P1INTA + 10 are applied to the OR gate 2-524, and generate the permission signal MYACKR + via the signals PXINTA + and OR gate 2-522. The signals P0INTN + 10 and P1INTN + 10 are applied to the OR gate 2-528 and generate an impossible signal MYNAKR + via the signals PXINTN + 10 and OR gate 2-526.

The logic elements of FIG. 3 are conventional in design, for example, using those introduced in the second edition of the TTL Data Book for Design Engineers, published by Texas Instruments.

Level changing operations are described in detail in US Patent Application No. 879,858 associated with the present application.

4 shows the layout of the data address and address feeds and the appropriate control signals during the control feed of the command. The control signals for the normal interrupt, that is, the memory reference signal BSMREF +, the second half bus cycle signal BSSHBC +, the bus yellow fast interrupt signal BSYELO + and the interrupt resume signal BSRINT + are all 'low'. The address signals BSAD08-17 + represent the channel number of the destination CPU. The address signals BSAD18-23 + provide a function code. The data signals BSDT00-09 + provide the channel number of the source. The data signals BSDT10-15 + indicate the interrupt priority level number of the command.

When the CPU interrupt level change command signal BSRINT + is 'high', the address signals BSAD00-17 + again indicate the channel number of the destination CPU, and the address signals BSAD18-23 + indicate a function code indicating the level change. Since level changes are initiated by the CPU, the data signals BSDT00-09 + provide the channel number of the source CPU, and the data signals BSDT10-15 + provide the new interrupt priority level.

When the high speed interrupt control signal BSYELO + is 'high', the address signals BSAD08-17 + represent the channel number of the destination CPU, and the address signals BSAD18-23 + represent the function code with the high bit BSAD18 + 'high'. BSDT00-09 + provide the channel number of the source that is hexadecimal OF for SMF 20.

For the reset fast interrupt busy command, the control signals BSYELO + and BSRINT + are 'high'. The CPU, which resets its busy flop, generates its own channel number and 'high' data signal BSDT9 +.

CPU0 (4-2) issues this command to reset the flop (2-554), and CPU1 (4-4) issues an instruction with its channel number to reset the flop (2-546). Send it out. By resetting the flops, the CPU can receive the next high-speed interrupt command.

While the present invention has been described with reference to preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and outline of the present invention.

Claims (6)

Multiple interrupting units and multiple processing units are commonly coupled to a system bus that asynchronously delivers commands during different operational bus cycles between the multiple interrupting units and each of the multiple processing units. 10. A data processing system in which the plurality of respective interrupting units are coupled to the bus and have instruction generating means for issuing the instructions to the bus during operation bus cycles assigned to the processing unit. The command includes an address feed coded to define a channel number indicating an address of the processing unit for receiving the command, and a control reference signal including a memory reference signal indicating that the address feed is coded to define the channel number. Phase 1, which defines the yield and normal interrupt Of and including the interrupt signal from the second state to define the type of interrupt signals and high speed interrupt; Channel decoder means coupled to the bus for detecting an output of the channel number assigned to the processing unit and the memory reference signal to the bus by any one of the processing units to generate an output signal; Coupled to the bus and the channel decoder means, the processing unit executing the command in response to the interrupt type signal in the second state that defines the fast interrupt, and the output signal and the busy signal in the first state Array means for generating together a first enable signal and a set busy signal representing a; Busy means coupled to said bus and said array means and including flop means for generating said busy signal in a second state in response to an address signal and said set busy signal included in said command; Said array means being coupled to said bus, said channel decoder means and said busy means, said interrupt type signal in said second state, said output signal from a continuous command and said busy signal in said second state To generate a first disable signal indicating that the processing unit is not executing the instruction; Further, coupled to the array means and the bus, sending a permission response signal to the interrupting unit in response to the first permission signal, or sending a disable response signal to the interrupting unit in response to the first permission signal. And a response means. 2. The apparatus of claim 1, wherein said array means further generates a comparison signal in response to said interrupt type signal and said output signal in said first state that define said normal interrupt; Each of said plurality of interrupting units is coupled to said bus and said array means from said instructions coded to define an interrupt priority level for comparison with an interrupt priority level of a command currently being executed by said processing unit. In response to data feed signals, generating a second grant signal if the interrupt priority level is higher than the current interrupt priority level, wherein the interrupt priority level is not higher than the current interrupt priority level. If it is further provided with a comparison means for generating a second impossible signal; The response means is coupled to the comparison means and the bus and generates the permission response signal in response to the second permission signal or generates the disable response signal in response to the second disable signal. Data processing system. 2. The data processing system according to claim 1, wherein said array means generates said set busy signal in response to said interrupt signal in said second state and said output signal from a reset bus command. 4. The apparatus according to claim 3, wherein said busy means comprises register means coupled to said array means and said bus, for generating a reset flop signal in response to data set from said set busy signal and said reset command, The flop means is coupled to the register means and generates the bus signal in the first state in response to the reset flop signal. Multiple units 4-2, 4-4, 12, 14 are coupled together for communication, at least one of the units 4-2, 4-4 being of the above-described priority level for execution at a particular time. Is a processing unit that executes a predetermined process among a plurality of different processes each assigned to each other, each of which is a request process (BSAD 18-23) and a priority of the requesting process to the processing unit at least when requesting a process to be executed by the processing unit. Delivers instructions with a description of the level (BSDT 10-15), wherein the first device (2-506, 2-550, 2-552) receives the instructions and prioritizes the processor currently running by the processing unit. Compare the priority level with the request priority level and if the request priority level is greater than the current level, inform the requesting unit of the request grant (BSACKR) and stop the execution of the current process. A lock signal MYACKR is generated to initiate execution of the request process, and the second device enables the requesting unit so that the processing unit does not consider the priority level of the request process or the priority level of the currently running process. In a data processing system which immediately executes a request process without a request, one of the units sends a description of a single interrupt signal (BSYELO) and a request process (BSAD 18-23) to the processing unit when the processing unit requests to execute the process immediately. Convey; In response to the single signal, logic circuits 2-506, 2-520, 2-522, and 2-530 immediately inform the requesting unit of the acknowledgment (BSACKR) and the processing unit immediately stops executing the current process so that the request can be made. Generating a signal (MYACKR) to initiate execution of the process. 6. The apparatus of claim 5, wherein the second device further conveys an identification (BSAD 08-17) of the processing unit required when the one unit requires the processing unit to execute the process immediately; An additional logic circuit of the processing unit which receives the identification and sends an additional signal CHANOK if the identification is identical to the identification of the processing unit, and generates the permission upon receipt of the single signal and the additional signal. Data processing system, characterized in that.

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