KR930003576A - Decoder for Multiplexer Control - Google Patents
Decoder for Multiplexer Control Download PDFInfo
- Publication number
- KR930003576A KR930003576A KR1019910011624A KR910011624A KR930003576A KR 930003576 A KR930003576 A KR 930003576A KR 1019910011624 A KR1019910011624 A KR 1019910011624A KR 910011624 A KR910011624 A KR 910011624A KR 930003576 A KR930003576 A KR 930003576A
- Authority
- KR
- South Korea
- Prior art keywords
- output
- gate circuit
- multiplexer control
- decoder
- transistors
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
Abstract
내용 없음.No content.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명의 기술적 원리를 도시한 디코더 회로,2 is a decoder circuit showing the technical principle of the present invention;
제3도는 본 발명에 따른 멀티 플렉서 제어용 디코더 회로.3 is a decoder circuit for multiplexer control according to the present invention.
Claims (1)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910011624A KR930003576A (en) | 1991-07-09 | 1991-07-09 | Decoder for Multiplexer Control |
GB9206957A GB2257875A (en) | 1991-07-09 | 1992-03-31 | Analogue decoder circuit for controlling a multiplexer |
JP4088482A JPH05122083A (en) | 1991-07-09 | 1992-04-09 | Analogue decoder circuit |
DE4212811A DE4212811A1 (en) | 1991-07-09 | 1992-04-16 | ANALOG DECODER CIRCUIT |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910011624A KR930003576A (en) | 1991-07-09 | 1991-07-09 | Decoder for Multiplexer Control |
Publications (1)
Publication Number | Publication Date |
---|---|
KR930003576A true KR930003576A (en) | 1993-02-24 |
Family
ID=19316984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910011624A KR930003576A (en) | 1991-07-09 | 1991-07-09 | Decoder for Multiplexer Control |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH05122083A (en) |
KR (1) | KR930003576A (en) |
DE (1) | DE4212811A1 (en) |
GB (1) | GB2257875A (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2198012B (en) * | 1986-11-20 | 1990-07-04 | Sony Corp | Clock signal multiplexers |
-
1991
- 1991-07-09 KR KR1019910011624A patent/KR930003576A/en not_active Application Discontinuation
-
1992
- 1992-03-31 GB GB9206957A patent/GB2257875A/en not_active Withdrawn
- 1992-04-09 JP JP4088482A patent/JPH05122083A/en active Pending
- 1992-04-16 DE DE4212811A patent/DE4212811A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH05122083A (en) | 1993-05-18 |
GB2257875A (en) | 1993-01-20 |
DE4212811A1 (en) | 1993-01-14 |
GB9206957D0 (en) | 1992-05-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |